Zero-Phase Filter Bank and Wavelet Code r Matrices: Properties,Triangular Decompositions,and a Fast Algorithm

The class of digital filter banks (DFB's) and wavelets composed of zero-phase filters is particularly useful for image processing because of the desirable filter responses and the possibility of using the McClellan transformation for two-dimensional design. In this paper unimodular polyphase matrices with the identity matrix for Smith canonical form are introduced, and then decomposed to a product of unit upper and lower triangular or block-triangular matrices which define ladder structures. A fundamental approach to obtaining suitable unimodular matrices for one and two dimensions is to focus on the shift (translation) operators, as is done in the harmonic analysis discipline. Several matrix shift operators of different dimensions are introduced and their properties and applications are presented, most notable of which is that the McClellan transformation can be effected by a simple substitution of a 2 × 2 circulant matrix for the polynomial variable, w = (z + z ^-1)/2. Unimodular matrix groups and pertinent subgroups are identified, and these are observed to be subgroups of the special linear group over polynomials, SL(k[w]) . A class of coiflet-like wavelets containing the well-known wavelet, based on the Burt and Adelson filter, is decomposed by these methods and is seen to require only 3/2 multiplications/sample if a scaling property, introduced herein, is satisfied. Making use of certain paraunitary wavelets, coiflets, that are closely comparable to the zero-phase wavelets of this class, it is seen that, in these cases, the zero-phase ladder algorithm is twice as fast as the paraunitary lattice algorithm.     

基于DSP的多相滤波正交数字下变频

数字下变频(DDC)是中频数字接收机的关键技术,通过将宽带大数据流变成窄带低数据流,以便DSP实时处理。本文提出一种基于多相滤波结构的正交数字下变频方案,通过计算机和DSP仿真,证明了它的可行性。     

考虑布局因素的射频CMOS多相位滤波器的优化与合成

开发了一个新颖的考虑布局因素的用于射频CMOS多相位滤波器的优化和合成工具--PPFOPTIMA.在优化引擎中使用了遗传算法用来避免局部的优化解.实验结果证明PPFOPTIMA是射频CMOS多相位滤波器设计和优化中有效的计算机辅助设计工具.     

Design and implementation of anti-windup controller based on stated feedback H∞ control theory

In the control of an actual plant, there commonly exists a constraint on the control input caused by mechanical constraint on the actuator or in order to protect the plant. This constraint usually exerts an adverse effect on control performance, called windup phenomenon. Anti-windup technique is known as one of the most effective techniques to prevent such windup phenomenon. In this paper, we propose a new design of anti-windup controller based on state feedback H^∞ control theory. This design consists of representation of an anti-windup controller that includes a free parameter, and decision of the free parameter by using state feedback H^∞ control theory. We also discuss the problem on discretization of an anti-windup controller in implementation. In a numerical case study, we demonstrate the performance of the proposed anti-windup controller by computer simulation. © 1998 Scripta Technica, Electr Eng Jpn, 124(1): 33–41, 1998     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Orthogonal superimposed training design for block transmission over frequency‐selective fading channels

Channel estimation for single‐carrier block transmission over frequency‐selective fading channel using superimposed training is addressed. A novel affine precoding model based on orthogonal polyphase sequence set is designed to decouple channel estimation from symbol detection. The orthogonal constraints on the training and precoding matrices ensure the separation of superimposed signals and accurate channel estimation with less training overheads as compared with time‐multiplexed scheme. Simulation results show that the proposed scheme exhibits good performance and outperforms another data‐dependent superimposed training scheme, especially for compact constellations or channel with long delay‐spread. Copyright © 2014 John Wiley & Sons, Ltd.     

求解非负矩阵分解的子空间共轭梯度算法

交替最小二乘法由于其理论可靠性和实际有效性成为非负矩阵分解中备受欢迎的方法之一。文中基于交替最小二乘法将界约束优化中的积极集共轭梯度法运用到非负矩阵分解当中,算法在子问题的求解中,并利用子空间的思想来划分指标集,并利用文献CHENG Wangyou文中的共轭梯度法进行变量更新,在一定条件下证明了新算法的收敛性,实验结果表明算法是有效的。     

局域零相关多相码设计

针对已有波形设计方法其旁瓣峰值经常出现在主瓣附近,而实际应用中目标回波可能跨越多个距离单元的情况,给出发射信号的自相关和互相关在主瓣附近具有零相关区域的两种波形方法。一种是基于遗传算法的类零相关多相码设计方法,该方法适用于离散相位的多相码设计;另一种是采用循环算法的设计方法,该方法适用于连续相位的多相码设计。两种方法都可以使主瓣附近一定区域内具有较低的旁瓣峰值。最后计算机仿真验证了两种方法的有效性。     

超宽带数字下变频器

在宽带数字接收机中,高速数据流的实时处理对后继数字下变频器性能提出了极为苛刻的要求。在多相滤波器结构的基础上,提出了采用多路并行乘法器的方法,大大提高了数字下变频器的输入数据流速率和数据带宽,最后给出了仿真结果。     

基于投影梯度的NMF相关反馈医学图像检索算法

相关反馈技术是近年来在图像检索中较为重要的研究方法,由于有人的参与,它能在一定程度上弥补图像的底层特征难以表达图像语义内容的不足.由于NMF在一定程度上勾勒出了相关图像在基矩阵所代表的空间中的分布,因而对整个图像库进行检索时可以查找到更多的相关图像.提出了一种基于投影梯度的非负矩阵分解(NMF)相关反馈方法,与常用的基...