基于供应链管理的供应商选择问题初探

首先讨论了供应链环境下选择供应商的意义，然后建立了供应商选择的评价指标体系，重点讨论了应用TOPSIS 方法对供应商选择的模型及算法，最后用一个简单的案例进行了说明。     

Growth of CeO_2, Y_2O_3 Buffer Layers for YBCO Coated Conductor

~~Growth of CeO_2, Y_2O_3 Buffer Layers for YBCO Coated Conductor     

刮板输送机接链用千斤拉的研究

针对刮板输送机的掐链、接链问题,研制出新型掐、接链用千斤拉,介绍了该装置的结构特点和工作原理,并对使用效果进行了分析。     

丙烯酸高碳醇酯的合成

介绍了降凝剂中间体丙烯酸高碳醇酯的合成和产品分离提纯方法。考察了合成条件对酯化反应的影响，结果表明，在原料丙烯酸与十八醇摩尔比1．2：1，阻聚剂对苯二酚用量占原料总量1．5％，催化剂对甲苯磺酸用量占原料总量1．5％，反应温度80-86℃，回流反应时间6h条件下，酯化率最高达89％。产品分离提纯方法与传统分离方法比较，所需分离时间短，洗涤用水量少，而产品收率远高于传统分离方法，达95％以上。     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.     

An introduction to Wu's method for mechanical theorem proving in geometry

Wu's algebraic method for mechanically proving geometry theorems is presented at a level as elementary as possible with sufficient examples for further understanding the complete method.The work reported here was supported by NSF Grant DCR-8503498.     

PARASITIC TOLERANT DIFFERENTIAL SC TRANSCONDUCTANCE USING UNITY GAIN BUFFERS

The unity gain buffer will be good to design high frequency SCF if its resistiveeffects can be eliminated,and therefore the whole parasitic sensitivities will greatly be reduced.On the basis of this concept,a novel parasitic tolerant SC DTE(differential transconductanceelement)is proposed.SC floating inductor and integrator fit for high frequency applications areformed by the DTE.The computer simulation and experiment on a third order elliptic LP filterverify its validity.     

一种高速浮点加法器的设计实现

浮点加法器是协处理器的核心运算部件，是实现浮点指令各种运算的基础，其设计优化是提高浮点运算速度和精度的关键途径。文章从浮点加法器算法和电路实现的角度给出设计方法，并且提出动态与静态结合设计进位链的方案以及前导O预测面积与速度的折衷方法。动态与静态结合设计进位链的方法有效地降低了功耗，提高了速度，改善了性能。目前已经嵌入协处理器的设计中，并且流片测试成功。     

酮亚胺对水性聚氨酯性能的改进

用丙酮分别和乙二胺、己二胺反应制备酮亚胺,并以其作为潜伏性扩链剂改善水性聚氨酯(PU)的性能。研究了酮亚胺以不同方式、加量对水性PU漆膜的厚度、硬度、耐水性、耐酸性、热稳定性和机械性能的影响。结果表明,采用丙酮缩乙二胺扩链的水性PU乳液的漆膜的耐水性优于用丙酮缩己二胺和用水扩链的PU乳液的漆膜,且加入过量的酮亚胺扩链效果较好,但其热稳定性并没有得到明显提高。     

基于Petri网的供需链设计优化研究

供需链设计优化问题由于其自身的复杂性而成为一个极具挑战性的研究课题。本文把Petri网与遗传算法结合起来，用于研究供需链设计优化，构建一个供需链原型测试系统，并对小汽车制造供需链系统进行了实例分析。