基于多曝光的高动态图像合成的噪声处理

针对在高动态范围图像合成的过程中有噪声影响图像的质量这一问题,采取一种基于多曝光图像的高动态范围图像合成降噪算法。通过对各曝光图像的灰度数据进行提取、整理、分析,能合成代表原始场景光线分布的亮度图像。通过分析噪声对高动态范围图像合成质量的影响,提出在图像合成前将图像中含有的噪声进行处理。根据光子散粒噪声变化的特点,将图像混有的噪声问题转化为求解一个多曝光图像序列组的平均值问题,合成的图像视觉效果与真实图像极为接近。     

GPS系统在车辆定位中的应用及测距算法的研究

本文研究了一种基于无线电思想的GPS接收机的实现方法，实现的整个过程都放在DSP内来完成，从而有效地节省了硬件资源，并且更加方便和灵活。介绍了GPS接收机在车载系统中的组成及应用。在设计时充分考虑了GPS接收机伪随机码测距的问题。此系统体现了简便、易控、模块化以及保密性好等优势。     

干涉光谱重建中的相位误差检测方法对比研究

干涉条纹相位误差检测与校正是傅里叶变换光谱重建中的关键技术之一。本文对同步 法、傅里叶变换法和局部傅里叶变换法三种典型干涉条纹相位误差检测方法的效果进行了对 比研究。仿真及实际数据实验发现上述方法在处理缓变与快变的干涉条纹相位误差及干涉条 纹有噪声时存在很大差异:同步法适宜于处理相位误差缓变的干涉条纹,而傅里叶变换法和 加窗傅里叶变换法适用于处理相位误差快变的情况;傅里叶变换法在高信噪比情况下具有较 好的性能,加窗傅里叶变换法在低信噪比下具有较强的鲁棒性。     

一种适用于卫星通信的低噪声放大器设计

采用高频电路仿真软件ADS,结合高频电磁仿真软件HFSS,进行联合仿真,设计了一种低噪声放大器,适用于Ku频段卫星通信接收通道。在频率11.45 GHz-12.75 GHz范围内,噪声系数小于0.80 dB,端口输入驻波小于-17.0 dB,有一定的实用价值。     

一种基于实时几何测距的船桥主动防撞方法

本文提出一种基于实时几何测距的船桥主动防撞方法.该方法对船的改动量甚微,仅需维持多项距离矩阵,通过告警逻辑矩阵进行展示与告警,能起到很好的船桥防撞提示效果.     

时域展宽特性对相关检测性能的影响分析

时域展宽是激光回波脉冲的重要特性,也是影响激光雷达相关检测性能的重要因素。建立了考虑时域展宽特性的激光回波脉冲数学模型,以此模型和相关检测原理为基础分析了时域展宽特性对相关检测测距误差、信噪比的影响,从激光发射脉冲的近高斯能量时间分布模型出发,推导了时域展宽系数的计算公式,并对理论分析和计算结果进行了仿真论证。仿真结果表明:回波脉冲时域展宽系数与其衰减系数成反比,与发射脉冲上升时间成正比,随着时域展宽系数的增大,激光雷达相关检测系统测距误差增大,信噪比降低。     

相干光OFDM系统中直接判决均衡器的性能研究

理论上分析了相干光正交频分复用(CO-OFDM)系统中相位噪声(PN)和色度色散(CD)对星座图的影响,并详细探讨了CO-OFDM系统中基于导频的直接判决均衡器(DDE)的原理,还对其性能进行了仿真分析。仿真结果表明:在不同的传输距离下,DDE的误码率都能呈瀑布状下降至10-3这一公认的前向纠错(FEC)门限,使得后续的FEC模块可以让误码率迅速降低。此外,在激光器线宽小于100kHz时,DDE的误码性能并没有大幅度的提升。因此,在选择DDE作为均衡器的CO-OFDM系统中,应折中考虑激光器线宽和误码性能的关系,基于成本考虑建议采用100kHz激光器。     

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0.35μm CMOS technology are presented.A differentially controlled quadrature voltage-controlled oscillator (QVCO) is employed to generate quadrature (I/Q) signals.A second-order loop filter,with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost.The measured spot phase noise is –106.15dBc/Hz@1MHz.Close-in phase noise is less than -70dBc/Hz.The synthesizer consumes 13.5mA under a 3.3V voltage supply.The core size is 1.3mm×0.8mm.     

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.Maria da Gloria Cataldi Flores was born in Santa Maria, Brazil, in 1978. She received the electrical engineering degree in 2000 from Universidade Federal de Santa Maria (UFSM) and the M.S. degree engineering in 2003 from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then, she has been working as a design engineer in an EAS Supply brazilian company. Her main research interests include mixed-signal and analog testing and digital signal processing.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree engineering in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the M.Sc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr. Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible by courses in VLSI Architecture and is also thesis director. His main research interests are Integrated Circuit Architecture, Embedded Systems, Signal Processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.Felipe Ricardo Clayton received the B.S. degree in Electrical Engineering from State University of Campinas (UNICAMP), Brazil, in 1986. He worked at CPqD (Brazilian PTT R&D Center) till 1996 designing analog and mixed signal circuits for telecom and automotive applications. From 1997 to the second half of 1998, he worked at Instituto Superior Técnico (IST), Lisbon, Portugal, under the guidance of Prof. Carlos Azeredo Leme on development of CMOS RF circuits. Since October 1998 he had worked for Motorola SPS. Now he is head of the Power Managment Group at Freescale.Cristiano Benevento received his B.S. degree in Electrical Engineering from Universidade Estadual de Campinas (Unicamp), Brazil, in 1997. He worked at Motorola Cellular Infrastructure Group until August 2000 as a Systems Engineer. He joined Motorola Semiconductor Product Sector in August 2000 as IC Designer for Power Management Group and is now at Freescale.     

非高斯噪声下的一种自适应IIR滤波算法

给出一种用递归总体最小平均P-范数法来实现IIR滤波器的估计,在估计中采用power迭代法,并应用矩阵求逆引理克服了直接求逆的繁琐计算,在文章的最后给出计算机仿真,显示了该算法性能的优越性。