Improving Throughput of Transmission Control Protocol Using Cross Layer Approach

Most of the internet users connect through wireless networks. Major part of internet traffic is carried by Transmission Control Protocol (TCP). It has some design constraints while operated across wireless networks. TCP is the traditional predominant protocol designed for wired networks. To control congestion in the network, TCP used acknowledgment to delivery of packets by the end host. In wired network, packet loss signals congestion in the network. But rather in wireless networks, loss is mainly because of the wireless characteristics such as fading, signal strength etc. When a packet travels across wired and wireless networks, TCP congestion control theory faces problem during handshake between them. This paper focuses on finding this misinterpretation of the losses using cross layer approach. This paper focuses on increasing bandwidth usage by improving TCP throughput in wireless environments using cross layer approach and hence named the proposed system as CRLTCP. TCP misinterprets wireless loss as congestion loss and unnecessarily reduces congestion window size. Using the signal strength and frame error rate, the type of loss is identified and accordingly the response of TCP is modified. The results show that there is a significant improvement in the throughput of proposed TCP upon which bandwidth usage is increased.     

Central Aggregator Intrusion Detection System for Denial of Service Attacks

Vehicle-to-grid technology is an emerging field that allows unused power from Electric Vehicles (EVs) to be used by the smart grid through the central aggregator. Since the central aggregator is connected to the smart grid through a wireless network, it is prone to cyber-attacks that can be detected and mitigated using an intrusion detection system. However, existing intrusion detection systems cannot be used in the vehicle-to-grid network because of the special requirements and characteristics of the vehicle-to-grid network. In this paper, the effect of denial-of-service attacks of malicious electric vehicles on the central aggregator of the vehicle-to-grid network is investigated and an intrusion detection system for the vehicle-to-grid network is proposed. The proposed system, central aggregator–intrusion detection system (CA-IDS), works as a security gateway for EVs to analyze and monitor incoming traffic for possible DoS attacks. EVs are registered with a Central Aggregator (CAG) to exchange authenticated messages, and malicious EVs are added to a blacklist for violating a set of predefined policies to limit their interaction with the CAG. A denial of service (DoS) attack is simulated at CAG in a vehicle-to-grid (V2G) network manipulating various network parameters such as transmission overhead, receiving capacity of destination, average packet size, and channel availability. The proposed system is compared with existing intrusion detection systems using different parameters such as throughput, jitter, and accuracy. The analysis shows that the proposed system has a higher throughput, lower jitter, and higher accuracy as compared to the existing schemes.     

无线传输中一种基于节能的多位纠错算法

在分析基于循环冗余校验码纠正单比特错误和基于CRC/BCH混合编码方法的基础上,提出了一种多位纠错算法,在一定的信噪比范围内分析了算法的纠错性能和对吞吐量的改善情况,算法降低了传输数据的误码率和误帧率,提高了系统的吞吐量.对纠错算法的能耗进行了分析比较,与ARQ方案,BCH纠错方案的能耗进行了对比,在一定的范围内算法有较高的能量利用率.     

基于无线网络的混合业务资源调度算法

WCDMA系统混合业务下的资源调度算法要区分业务以保证用户的服务质量(QoS)。基于此,在研究最大加权延时优先算法(M-LWDF)的基础上通过引入QoS监测机制提出一种保证混合业务服务质量的资源调度算法,在业务调度中同时考虑时延优先级和吞吐量优先级,并采用传输时延保证的资源分配准则。仿真结果表明,该算法在时延和吞吐量水平上要优于已有的调度算法。     

空基自组网中基于负载均衡的路由策略

针对空基网中节点负载失衡以及吞吐量低下的问题,提出基于负载均衡的优化路由协议。该协议在获得位置信息的前提下,预测出通信链路的有效时间,在满足数据的时延、带宽以及链路有效性等多约束条件下,以均衡节点负载为优化目标,使得网络节点都能合理承担数据传输任务。仿真结果表明,该路由协议能够保证网络节点合理分担传输任务,充分利用链路资源,从而提高网络的吞吐量。     

基于指令相对吞吐率的虚拟机检测方法

对于常见的虚拟机检测方法仅适用于特定配置的虚拟机的不足,设计并实现一种基于特权指令与非特权指令的相对吞吐率变化的检测虚拟机的方法,检测过程采用查询-验证的方式。该方法可以成功地分辨出物理机环境与虚拟机环境的不同,并且事先只需了解较少的待检测目标的配置信息,对不同硬件配置的依赖性较小。     

FPGA implementation and performance evaluation of a high throughput crypto coprocessor

This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).