On the design considerations of solid-state power amplifiers for satellite communications: A systems perspective

Conventional solid-state power amplifier (SSPA) design approach isolates radio frequency (RF) design from communication theory. In this paper, a unified SSPA design approach is proposed, which optimizes SSPA parameters (bias voltage and input RF signal power) to minimize total DC power consumption while satisfying received SNR constraint specified by the link budget. The effect of SSPA nonlinearity is quantified by the error vector magnitude measured at its output and the corresponding received SNR degradation is analyzed. Using the quantitative metrics for received SNR, it is possible to evaluate highly nonlinear SSPA classes such as Class-B or deep-Class AB, which are normally not considered in conventional SSPA design approach to be used in satellite communication applications.     

Multi-Stage CMOS OTA Frequency Compensation: Genetic algorithm approach

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 μm. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 μW.     

微波、毫米波GaN HEMT与MMIC的新进展

综述了近几年微波、毫米波氮化镓高电子迁移率晶体管(GaN HEMT)与单片微波集成电路(MMIC)在高效率、宽频带、高功率和先进热管理等方面的应用创新进展.介绍了基于GaN HEMT器件所具有的高功率密度和高击穿电压,采用波形工程原理设计的各类开关模式的高效率功率放大器,以及基于GaN HEMT器件的高功率密度、高阻抗的特点与先进的宽带拓扑电路和功率合成技术相结合的宽频带和高功率放大器.详细介绍了微波高端和毫米波段的高效率、宽频带和高功率放大器,多功能电路和多功能集成的GaN MMIC.最后阐述了由于GaN HEMT的功率密度是其他半导体器件的数倍,其先进热管理的创新研究也成为热点.     

一种输入输出轨到轨CMOS运算放大器的设计

随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18 μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 mV到电源电压减去50 mV,实现了输入输出轨到轨的目标。     

EWB软件在电子实验中的应用

计算机仿真工具层出不穷,但作为虚拟的电子工作平台,Electronics Workbench即EWB界面直观、操作方便,选用元器件和仪器最接近实际情形。介绍了计算机仿真软件EWB(虚拟电子工作室),列举了该软件在模拟电路仿真、数字电路仿真实验中的应用实例,得出了在电子实验中引入EWB,可以解决实验室条件受限的困难,还可大大提高效率,并使其实验的内容与形式更加丰富更有新意。     

基于AVR ATmega169的张力检测仪设计

分析应变测量原理,应用应变片敏感栅作为传感器,结合仪表放大器电路和高集成度的单片机ATmega169实现低功耗便携式张力测试仪的设计。该系统功耗低、测量准确、直接数字读出,具有多种附加功能。成功解决了由经验判断引起的偏误过大问题。给出在实际应用中硬件电路和软件程序的实现方案。分析设计中常见的问题,并给出解决问题的思路。对相关的测量仪表设计、开发有一定参考作用。     

Two new analog multipliers/dividers employing single current differencing buffer amplifier

This paper presents two new analog multipliers/dividers using a new universal active element, called the current differencing buffered amplifier (CDBA). The reported circuits are suitable for monolithic chip realization for use in battery-powered, portable electronic equipments. The circuits can be used as a multiplier and divider without changing circuit topologies. The workability of the proposed configurations is tested through different applications with PSPICE simulations using TSMC 0.35 μm CMOS process parameters. The simulated results show that: for ±2.5 V power supply, the total harmonic distortions are less than 3.1% and 2.25% for the first and second configuration respectively. It also shows that the −3 dB bandwidths are 59.09 MHz and 68.55 MHz and static power dissipations are 0.28 mW and 0.23 mW respectively. The sensitivity of the output of the circuits is low with respect to temperature variations.     

CdSe/ZnS量子点掺杂聚合物光纤放大器增益特性分析

提出了一种半导体量子点CdSe/ZnS掺杂聚合物光纤放大器。测量了CdSe/ZnS量子点吸收和发射光谱,采用二能级结构和速率方程的方法,全面描述了CdSe/ZnS量子点掺杂聚合物光纤放大器的增益性能。计算了放大器增益随量子点掺杂光纤长度、量子点掺杂浓度和信号光强度的变化,给出了不同泵浦光强条件下的增益谱线及半高全宽。结果表明,在mW量级的泵浦条件下,CdSe/ZnS量子点掺杂聚合物光纤放大器可获得35dB以上的增益,获得相同增益所需泵浦光强度只有同类型染料掺杂聚合物光纤放大器的万分之一。泵浦光强与量子点掺杂浓度之间存在最佳对应关系,单位泵浦功率激发的最佳量子点数为6.33×107/mW。在室温下,CdSe/ZnS量子点掺杂聚合物光纤放大器具有550nm～610nm的带宽,含盖了聚合物光纤的低损窗口。     

抽运功率配置对双向喇曼放大器性能的影响

为了研究抽运功率配置对双向抽运光纤喇曼放大器性能的影响,基于已有的耦合方程,采用数值仿真方法,分析了不同抽运功率配置对双向抽运光纤喇曼放大器的增益、增益饱和以及抽运功率转换效率的影响。结果表明,双向抽运光纤喇曼放大器的增益、增益饱和以及抽运功率转换效率特性均介于同向和反向抽运光纤喇曼放大器之间,并且随着同向抽运功率在抽运总功率中所占比例的升高,增益、增益饱和功率和抽运功率转换效率的数值增加;大信号、抽运功率较大时,抽运功率配置对双向抽运光纤喇曼放大器性能的影响显著。这对双向抽运光纤喇曼放大器和光纤激光研究具有一定的参考价值。     

单偏振半导体光放大器扫频光相干层析系统

实现了基于单偏振半导体光放大器高速扫频光源的光相干层析系统。系统中的扫频光源使用偏振相关的半导体光放大器,采用傅里叶域锁模结构。偏振相关的半导体光放大器有着增益谱宽大、输出功率高的优点,使得光源仅使用一个放大器即可获得足够的增益谱宽与输出功率。扫频光源输出功率达到32mW左右,有效扫描频率为45kHz,输出光谱的中心波长为1 326nm,光谱宽度为115nm。利用系统进行光相干层析成像时,横向分辨率为9μm,纵向分辨率为12.9μm左右,灵敏度为105dB。利用该系统实现了多种生物和非生物样品的光学相干层析成像。