静态时序分析中的门延时计算

静态时序分析由于速度快和容量大而广泛应用于时序验证,而门延时的计算则是静态时序分析中的关键部分。以前利用等效输出驱动点导纳函数相等原理产生的模型,由于不能很好的与等效电容公式结合,门延时的计算存在过于悲观性或乐观性结果。本文采用输出驱动导纳和互连线拓扑结构相结合的方法, 对门延时负载模型进行了改进,很好地与等效电容计算结合,保证了静态时序分析的准确性。     

A framework for delivering fine granularity and fair service discrimination in DiffServ networks

In order to achieve a quality of service (QoS) capable of satisfying an ever increasing range of user requirements, differentiated services (DiffServ) have been introduced as a scalable solution that emerges ‘naturally’ from today's best effort service approach. Mapping the packet treatment into a small number of per hop behaviours (PHBs) is the key idea behind the scalability of DiffServ but this comes at the cost of loosing some behavioural differentiation and some fairness between flows multiplexed into the same aggregated traffic. The paper proposes a novel simple and effective DiffServ approach, the ‘Simple Weighted Integration of diFferentiated Traffic’ (SWIFT), and uses it in a series of simulations covering a relatively wide range of local network conditions. Measured voice and video traffic traces and computer generated self‐similar background traffic were used in simulations performed at various congestion levels and for in‐profile and out‐of‐profile source behaviour. The resulted throughput, mean delay, maximum delay and jitter are used to asses SWIFT's capabilities—isolation of the in‐profile traffic from congestion effects, treatment differentiation, increased resource utilization, fairness in treatment under congestion, and incentivity for nice behaviour. Comparisons with other approaches employing traffic control are also provided. Copyright © 2003 John Wiley & Sons, Ltd.     

ON THE STABILITY OF A THRESHOLD AR(1) WITHOUT INTERCEPTS

Abstract. Binary polynomials are used to determine the stability of a threshold AR(1) without intercepts.     

The Effect of Signal Activity on Propagation Delay of CMOS Logic Gates Driving Coupled On-Chip Interconnections

The effect of interconnect coupling capacitances on neighboring CMOS logic gates driving coupled interconnections strongly depends upon signal activity. A transient analysis of two capacitively coupled CMOS logic gates is presented in this paper for different combinations of signal activity. The uncertainty of the effective load capacitance and propagation delay due to signal activity is addressed. Analytical expressions characterizing the output voltage and propagation delay are also presented for different signal activity conditions. The propagation delay based on these analytical expressions is within 3% as compared to SPICE, while the estimated delay neglecting the difference between the load capacitances can exceed 45%. The logic gates should be properly sized to balance the load capacitances in order to minimize any uncertainty in the delay and load. The peak noise voltage on a quiet interconnection determined from the analytical expressions is within 4% of SPICE. The peak noise voltage on a quiet interconnection can be minimized if the effective output conductance of the quiet logic gate driving the interconnect is increased.     

Radiolocation in CDMA Cellular System Based on Joint Angle and Delay Estimation

This paper considers the problem of wireless location in code-divisionmultiple-access (CDMA)cellular system. Through the method of jointly estimating angle of arrival(AOA) and time ofarrival (TOA), a novel scheme is proposed for radiolocation in multipathenvironment, especiallywhen line-of-sight (LOS) path is not available to every base station involvedin location servicefor a mobile subscriber. The Cramer-Rao bound (CRB) is derived for the jointestimator. Based onsimulation results, the accuracy of the proposed wireless location scheme inCDMA system is assessed.     

A Test Methodology for High Performance MCMs

Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, andreliability benefits of MCMs. These advantages are only realized,however, if accompanied by an efficient test strategy whichverifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs thathave been mounted onto a multi-chip silicon substrate. A teststrategy, which addresses testing from the wafer level through tothe populated substrate, is detailed. This strategy uses acombination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high testquality at a reasonable cost. The methodology is then contrastedto alternative approaches.     

被动声探测系统的时间延迟估计技术

综述了被动声探测系统的时延估计方法，分析了现有时延估计方法的优缺点，结合国内外研究现状，评述了被动声探测系统时延估计技术的发展。     

光纤环形延迟线陷波器最佳陷波的实现及PIIN的影响

本文研究了ＰＩＩＮ的时，频响应特性，得到了它作为陷波器的最佳陷波条件，提出了利用环路损耗调节器性能，实现最佳陷波特性的方法，采用该方法使ＦＯＲＤＬ的陷波深度达到了６５ｄＢ，同时，本文还研究限制ＦＯＲＤＬ最佳陷波特性实现的主要系统因素－相位感生的强度噪声（ＰＩＩＮ）给出其在单模条件下的频率特性，由此出发，分析了影响ＰＩＩＮ的几个因素，提出了抑制ＰＩＩＮ的三个途径：（１）采用极化控制器适当调节两个正交     

B—DMB快速分组交换机的性能分析

由于不能预先对进入B-DMB交换机的各分组进行调整,可能出现同一时隙有2个或2个以上的分组都要到达某一输出端的情形,因此在B-DMB交换机中不可避免地要加进一些缓冲器。本文对B-DMB交换机的输入、输出缓冲器长度和分组时延进行了分析和计算,得出了一些有用的结论。