Design of Feedback Shift Register of Against Power Analysis Attack

Stream ciphers based on linear feedback shift register (LFSR) are suitable for constrained environments, such as satellite communications, radio frequency identification devices tag, sensor networks and Internet of Things, due to its simple hardware structures, high speed encryption and lower power consumption. LFSR, as a cryptographic primitive, has been used to generate a maximum period sequence. Because the switching of the status bits is regular, the power consumption of the LFSR is correlated in a linear way. As a result, the power consumption characteristics of stream cipher based on LFSR are vulnerable to leaking initialization vectors under the power attacks. In this paper, a new design of LFSR against power attacks is proposed. The power consumption characteristics of LFSR can be masked by using an additional LFSR and confused by adding a new filter Boolean function and a flip-flop. The design method has been implemented easily by circuits in this new design in comparison with the others.     

储层随机建模研究进展

按照模拟网格不同储层随机建模技术可以分为基于目标的方法和基于象元的方法2类。介绍了基于目标方法中的布尔模拟方法及其改进,这些改进包括井间和井上模拟时采取不同的概率分布、模拟多个岩相单元、模拟具有波动顶底的目标、综合地震数据、采取Gibbs分布的广义示性点过程模拟目标之间相互影响以及采用线模型模拟河道的目标层次建模(Fluvsim)。论述了基于象元方法中的新方法,指出多点地质统计学比传统的两点统计学具有明显优势,分析了多点地质统计学存在的问题及其改进方向(平稳性问题处理、目标体连续性处理、数据样板选择、综合地震信息方面)。最后评述了储层随机建模的发展方向,指出在目标之间相互影响函数的确定、获取反应实际储层结构特征参数、先验概率求取以及随机模拟结果评价方面有待进一步研究。     

基于布尔可满足性的逻辑电路等价性验证方法

提出了基于布尔可满足性(Boolean Satisfiability,SAT)的逻辑电路等价性验证方法。这一验证方法把每个电路抽象成一个有穷自动机(FSM),为两个待验证的电路构造积机,把等价性验证问题转换成了积机的断言判定问题。改进了Tseitin变换方法,并将其用于把电路约束问题变换成(Conjunctive Normal Form,CNF)公式。之后则用先进的CNF SAT求解器zChaff判定积机所生成的布尔公式的可满足性。事例电路验证说明了该方法的有效性。     

Boole语义的程度化方法

基于B-赋值理论,通过在Boole赋值格和全体公式集上分别建立概率测度,利用积分方法提出了Boole语义上公式的B-概率真度,进而在Boole语义上建立了概率逻辑度量空间,将计量逻辑学中近似推理方法推广到Boole语义上,完善了Boole语义的程度化方法.     

布尔函数与图论结合在系统可靠性分析中的应用

提出了一种运用布尔函数与图论相结合，对系统进行可靠性分析的新方法。应用图论，可以表赢系统可靠性与各组成部件的相互关系；运用布尔函数，可以表现系统中特殊部件之间失效的相互影响作用：将这些关系和作用进一步地综合，就可以对整个系统进行分析。为说明该方法，结合具体事例进行了分析。     

Boolean operations of STL models based on loop detection

For the data processing of rapid prototyping manufacturing, Boolean operation can offer a versatile tool for editing or modifying the STL model, adding the artificial construction, and creating the complex assistant-support structure to meet special technical requests. The topological structure of STL models is built firstly in order to obtain the relationship among the triangular facets of the object. The intersection test between two triangles picked, respectively, from two solids is taken to get the intersection triangle pairs and the intersection segments array, from which the intersection segments loops are detected. The intersection surfaces are divided into several surface patches along the intersection loops. The inclusion prediction is taken by testing the candidate point whether inside or outside the solid region of the solid slice. Detecting the loops for determination of the valid intersection lines greatly increases the efficiency and the reliability of the process. An erratum to this article can be found at     

Single‐layer perceptron and dynamic neuron implementing linearly non‐separable Boolean functions

This paper presents a single‐layer perceptron (SLP) scheme with an impulse activation function (IAF) and a dynamic neuron (DN) with a trapezoidal activation function (TAF). Combining with some interesting properties of the offset levels, it is shown that many linearly non‐separable Boolean functions can be realized by using only one SLPwIAF or one DNwTAF. In the present work, a few appropriate IAF and TAF are adopted, and the inverse offset level method is used for the design of the SLPwIAF synaptic weights and the DNwTAF templates. The XOR and NXOR Boolean operations with two inputs and all 152 non‐separable Boolean functions with three inputs can be easily implemented by one SLPwIAF or one DNwTAF. Finally, the entire set of 152 DNwTAF templates associated with 152 non‐separable Boolean functions of three inputs is completely listed. Copyright © 2008 John Wiley & Sons, Ltd.     

n处自由投切电路状态的布尔函数分析判别

本文列出了n处自由投切电路的布尔真值表含表达式,详尽地分析了该电路的内在关系,乃一“同或”和“异或”门在投切下不断交替,揭示出函数为一偶数电路,可用有规律的有限个二阶变量矩阵连乘来表达,但其展开式十分冗长不便判别其函数值,当采用本文新定义的[0与门]运算判别,则可按二进制列出其表达式,立即判别其函数值,方法简便,且投切即构成逻辑关系,较典型的逻辑电路还要单一简化,可供设计逻辑电路时参考,本电路的实用性还在扩展中.