一种输入输出轨到轨CMOS运算放大器的设计

随着电源电压的日益降低,信号幅度不断减小,在噪声保持不变的情况下,信噪比也会相应地减小。为了在低电源电压下获得高的信噪比,需提高信号幅度,而输入输出轨到轨运算放大器可获得与电源电压轨相当的信号幅度。中文在理论分析了输入输出轨到轨CMOS运算放大器主要架构优缺点后,给出了一种新的输入输出轨到轨CMOS运算放大器的设计,该电路在华润上华0.18 μm工艺平台上流片验证。测试结果表明,输入范围从0到电源电压,输出范围从50 mV到电源电压减去50 mV,实现了输入输出轨到轨的目标。     

A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques

In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second- and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain, -3 dB bandwidth (BW_−3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of +13.1 dBm and +42.8 dBm, respectively. The simulated S₁₁ is less than −11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.     

A new CMOS differential current-mode AGC on the division operation based

A new CMOS differential current-mode AGC on the division operation based is presented. The operation principle consists in detection of both positive and negative envelopes of the differential input signal cycles, respectively. The output signal with constant magnitude is obtained by dividing the differential input signal to the difference between the positive and negative detected envelopes. The new current-mode architecture of the proposed AGC (composed only by an envelope detector and a divider stage) diminishes significantly the settling time, the circuit complexity and the power consumption. The circuit yields an input dynamic range of 15 dB and provides a constant magnitude output signal in the frequency range from 10 MHz to 70 MHz. The current consumption is 5 mA from a single 3.3 V supply voltage. The simulations performed in 0.13 µm CMOS process confirm the theoretically obtained results.     

A low power dissipation high-speed CMOS image sensor with column-parallel sigma–delta ADCs

A 60frames/s CMOS image sensor with column-parallel inverter-based sigma–delta (ΣΔ) ADCs is proposed in this paper. In order to improve the robustness of the inverter, instead of constant power supply, two buffers are designed to provide power supply for inverters. Instead of using of an operational amplifier, an inverter-based switch-capacitor (SC) circuit is adopted to low-voltage low-power ΣΔ modulator. Detailed analysis and design optimization are provided. Due to the use of the inverter-based ΣΔ ADCs, the conversion speed is improved while reducing the area and power consumption. The proposed CMOS image sensor has been fabricated with 0.18 μm CMOS process. The measurement results show that the random noise (RN) is 7e_rms⁻, the pixel conversion gain is 100 μV/e⁻. Since the measured full well capacity of the pixel is 25000e⁻, the CMOS image sensor achieves a 71 dB dynamic range (DR). The total power consumption at 60frame/s is 58.2 mW.     

两通道按列输出CMOS图像的非均匀性及校正方法

为确保航空遥感图像产品相对辐射质量,提出了一种对两通道按列输出CMOS(互补金属氧化物半导体)图像的非均匀性进行校正的方法。以美国仙童公司CMOS探测器CIS2521F为例,通过实验室积分球观测试验研究了暗电流噪声、平均灰度、两通道输出等因素造成的图像非均匀性;然后,基于实验室积分球观测数据,采用两点线性法,校正了由按列放大输出导致的列状条带噪声;接着,通过优化拼接线附近图像灰度差异统计结果,校正了两通道响应不一致造成的图像辐射差异。试验表明,单通道图像非均匀校正使积分球观测图像的平均非均匀度量值由4.4下降至2.4,两通道图像非均匀校正消除了两通道图像的目视差异。原始航空遥感图像经过非均匀性校正后,图像灰度均匀,能够满足遥感图像判读要求。     

一种低压、恒增益Rail-to-rail运算放大器的设计

文章设计了一种低压、恒定增益、Rail-to-rail的CMOS运算放大器。该放大器采用直接交迭工作区的互补并联输入对作为输入级,在2V单电源下,负载电容为25pF时,静态功耗为0.9mW,直流开环增益、单位增益带宽、相位裕度分别为74dB、2.7MHz、60°。     

基于0.5 μm CMOS集成电路高低压兼容技术研究

将高压MOSFETs器件集成到低压CMOS数字和模拟电路中的应用越来越频繁。文章参考了Parpia提出结构,将高压NMOS、PMOS器件制作在商用3.3V/5V 0.5μmN-阱CMOS工艺中,没有增加任何工艺步骤,也没有较复杂BiCMOS工艺中用到的P-阱、P+、N+埋层,使用了PT注入。通过对设计结构的PCM测试,可以得到高压大电流的NMOS管BVdssn>23V～25V,P管击穿BVdssp>19V。同时,文章也提供了高压器件的设计思路和结果描述。     

一种超低功耗电流反馈运算放大器

设计了一种新型的基于第二代电流传输器CCⅡ-的超低功耗电流反馈运算放大器,并采用TSMC0.6μmCMOS工艺,利用Hspice对整个电路进行了仿真。在±1.5V电源电压工作条件下,该放大器的转换速率达到28.57V/μs,并且在闭环工作状态下具有恒定的带宽。     

应用于802.11a的5.7GHz CMOS LNA设计

使用0.18μm CMOS工艺设计应用于802.11a WLAN的U-NII高频段5.7GHz的LNA.首先选取LNA结构,推导出噪声模型,然后选取在固定功率消耗下最小噪声系数对应的晶体管尺寸,再进行输入输出阻抗匹配和电路调整优化.在使用Bond Wire不加Pad时提供-22.014dB S11,-44.902dB S22,15.063dB S21,-39.44dB S12,2.453dB/2.592dB的噪声系数(NF),-4.1915dBm的三阶互调输入点(IIP3),-15.6dBm的功率1dB压缩点(P1dB)和10mW的功率消耗(Pd).完全考虑Bond Wire和Pad效应的性能参数也已经给出,但噪声系数恶化为3.21/3.23dB,S参数在电路调整优化之后变化不大,整体性能比较突出.