PDSOI体源连接环形栅nMOS特性研究

提出了一种基于部分耗尽绝缘体上硅的体源连接环形栅nMOS器件,并讨论了相应的工艺技术和工作机理。采用体源连接环形栅器件结构,有效地抑制了浮体环形栅器件中存在的浮体效应和寄生双极晶体管效应,使器件性能得到很大的提高。消除了浮体环形栅器件的反常亚阈值斜率和Kink效应,DIBL从120.7mV/V降低到3.45mV/V,关态击穿电压从4.8V提高到12.1V。最后指出,体源连接环形栅器件非常适合于抗辐照加固等应用领域。     

A Low Power SRAM/SOI Memory Cell Design

提出一种改进4管自体偏压结构SRAM/SOI单元. 基于TSUPREM4和MEDICI软件的模拟和结构性能的分析，设计单元结构并选取结构参数. 该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOS SRAM单元中的pMOS元件，具有面积小、工艺简单的优点. 该结构可以在0.5V的电源电压下正常工作，与6管单元相比，该单元瞬态响应正常，功耗只有6管单元的1/10，满足低压低功耗的要求.     

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.     

Active mode leakage reduction using fine-grained forward body biasing strategy

Leakage power minimization has become an important issue with technology scaling. Variable threshold voltage schemes have become popular for standby power reduction. In this work we look at another emerging aspect of this potent problem which is leakage power reduction in active mode of operation. In gate level circuits, a large number of gates are not switching in active mode at any given point in time but nevertheless are consuming leakage power. We propose a fine-grained forward body biasing (FBB) scheme for active mode leakage power reduction in gate level circuits without any delay penalty. Our results show that our optimal polynomial time FBB allocation algorithm results in 70.2% reduction in leakage currents. We also present an exact standard-cell placement driven FBB allocation algorithm that effectively reduces the area penalty using the post-placement area slack and results in 56.5%, 62.8% and 66.1% reduction in leakage currents for 0%, 4% and 8% area slack, respectively. Furthermore, we present a heuristic to solve the standard-cell placement driven FBB allocation problem that is computationally efficient and results in leakage within 2% of that from the exact formulation.     

Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology.We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.     

外源信号物质对肉苁蓉种子萌发体的影响研究

肉苁蓉（Cistanche deserticola Y.C.Ma）是沙生根寄生植物。采用激光扫描共聚焦显微镜（LSCM）,对种子经外源信号物质氟草敏（Norflurazon）、2,6-二甲氧基对苯醌（DMBQ）处理后萌发产生的类胚根状体、初生吸器的细胞形态;Ca2＋浓度、囊泡运输的变化情况进行了观察研究。结果表明,肉苁蓉种子萌发产生的类胚根状体顶部的细胞为多面体,细胞小,排列紧密,内含物较多,中部大多为长方形薄壁细胞,内含物少;经DMBQ处理后类胚根状体细胞的钙离子浓度升高,囊泡运输加强。研究结果为揭示外源信号物质对肉苁蓉寄生影响提供了理论依据。     

粉防己碱对血管性痴呆大鼠学习记忆能力及神经元凋亡的影响

目的：探讨粉防己碱（Tet）对血管性痴呆（VaD）大鼠学习记忆能力和海马神经元凋亡的影响。方法：将40只大鼠随机分为假手术组、模型组、Tet干预组（含10和30mg/kg两个剂量组）,采用双侧颈总动脉永久性结扎（2-VO法）建立VaD大鼠模型。造模12周后进行Morris水迷宫实验检测大鼠行为学,HE染色观察海马CAl...     

人体行走电压的时域波形研究

基于测试得到的人体行走电压时域波形,提出了仿真人体行走电压的等效电路模型构建方法,分析了模型参数对人体行走电压时域波形的影响.按照IEC 61340-4-5中规定的人体行走电压的测试方法,测试了不同温湿度、不同鞋、不同地板条件下,人体行走电压的时域波形.通过对大量实测人体行走电压时域波形的分析,提出了人体行走电压的等效RC电路模型,得到人体的带电量满足指数形式的充放电关系,其时间常数τ由等效电路模型的电阻R、电容C参数决定.人体行走中,人的动作引起人体电容的周期性变化,进而导致人体电压呈现周期性变化趋势.通过对比实测数据,模型与实验结果符合较好,人体动作引起的电压周期性变化一致性较好,实验具有很好的可重复性.     

基于ANSYS的智能搬运AGV小车下车体结构分析

本文以智能搬运AGV小车下车体机械结构为例,应用ANSYS12.0对智能搬运AGV小车下车体机械结构进行有限元分析,旨在校核该结构的合理性、可靠性;进而为新一代AGV小车车体机械结构的设计提供重要科学性保证。     

基于MC9S12XET256MAL的汽车车身控制模块系统电路设计

本设计是以Freescale导体的MC9S12XET256MAL设计车载车身控制单元,主要实现功能包含车窗控制,车灯控制,背光控制,RKE,雨刮,清洗电机,防盗报警,中控门锁,行车喇叭,安全指示灯,CAN总线,LIN总线。增强汽车的安全、舒适和方便性。用户可以对外部按键操作实现相应功能,同时采集相关传感器自动实现相关功能,例如雨刮,防盗报警。利用总线将显示系统、驾驶员信息系统、导航系统、计算机网络系统、状态监测与故障诊断系统等连接。