FPGA implementation and performance evaluation of a high throughput crypto coprocessor

This paper describes the FPGA implementation of FastCrypto, which extends a general-purpose processor with a crypto coprocessor for encrypting/decrypting data. Moreover, it studies the trade-offs between FastCrypto performance and design parameters, including the number of stages per round, the number of parallel Advance Encryption Standard (AES) pipelines, and the size of the queues. Besides, it shows the effect of memory latency on the FastCrypto performance. FastCrypto is implemented with VHDL programming language on Xilinx Virtex V FPGA. A throughput of 222 Gb/s at 444 MHz can be achieved on four parallel AES pipelines. To reduce the power consumption, the frequency of four parallel AES pipelines is reduced to 100 MHz while the other components are running at 400 MHz. In this case, our results show a FastCrypto performance of 61.725 bits per clock cycle (b/cc) when 128-bit single-port L2 cache memory is used. However, increasing the memory bus width to 256-bit or using 128-bit dual-port memory, improves the performance to 112.5 b/cc (45 Gb/s at 400 MHz), which represents 88% of the ideal performance (128 b/cc).     

A short and versatile finite element multiscale code for homogenization problems

We describe a multiscale finite element (FE) solver for elliptic or parabolic problems with highly oscillating coefficients. Based on recent developments of the so-called heterogeneous multiscale method (HMM), the algorithm relies on coupled macro- and microsolvers. The framework of the HMM allows to design a code whose structure follows the classical finite elements implementation at the macro level. To account for the fine scales of the problem, elementwise numerical integration is replaced by micro FE methods on sampling domains. We discuss a short and flexible FE implementation of the multiscale algorithm, which can accommodate simplicial or quadrilateral FE and various coupling conditions for the constrained micro simulations. Extensive numerical examples including three dimensional and time dependent problems are presented illustrating the efficiency and the versatility of the computational strategy.     

医院信息系统综合评价体系模型

为推动医院信息化建设工作的规范化,加强医院信息化建设的管理、监督、指导和评审工作,构建出一个具有广泛代表性的医院信息系统评价体系模型,使得我区医院信息化进程能够持续健康的发展. 我们运用一种改进的层次分析法原理,对指标体系中的每一个单一指标进行权重求解,从而得出一个可以求解出系统性能测试和功能测试总得分的指标体系,对医院信息系统进行综合评价. 通过该模型对新疆医科大学两家附属医院信息系统进行计算评分,最终科学有效地评价了该两家医院的信息系统,找出医院信息化工作的不足之处并给出了科学的改进建议.     

SQL执行计划与直方图关系研究

sql语句调优是数据库性能调优的重要方面.要达到同样的执行结果,sql语句有多种写法,不同的写法其性能差别很大.即使同一个sql语句,oracle也有多种途径去执行,即有多个执行计划.oracle比较这多个执行计划的性能优劣,耗费资源多少,来选择最优的执行计划.oracle在评估各个执行计划的性能时,需要借助sql语句执行的环境,即统计信息,来计算出每个执行计划耗费资源的多少.因此,尽可能收集准确的统计信息,对于oracle能否选择最优的执行计划,至关重要.其中,直方图的收集与否起着很重要的作用.本文通过实验来验证直方图对sql执行计划的影响,从而明确何种情况下需要收集直方图.     

项目教学在高职《音视频编辑与制作》课程中的探索与实践

以《音视频编辑与制作》课程为例,按照“以培养学生职业能力为核心,以实际工作过程为导向,以多媒体作品的制作流程为主线”的总体设计要求,构建和设计项目课程的教学内容,并对该课程在项目教学改革做了深入的探索与实践.     

《微机维修技术》课程教学改革实践

介绍了通过对《微机维修技术》这门课程进行教学改革实践,确定了本课程的课程目标、教学组织安排和考核内容与方法,并在教学组织安排中讲到了教学组织形式、课程实施、教师指导方法和教学效果等方面。通过实践,效果显著。     

动态模式识别算法的GPU平台实现

研究动态模式识别算法在GPU并行计算平台的实现。随着GPGPU(通用计算图形处理器)硬件的发展,基于GPU的大规模并行计算技术将有效地处理动态模式识别算法带来的海量计算问题。文中通过介绍动态模式识别算法,对算法中涉及的巨大计算量进行分析,并针对性地对其中密集计算部分进行并行化分解,移除原算法中在执行中存在的依赖关系,最终得到算法在特定的GPU平台———Jacket上的并行计算实现。实例验证表明,相比于原CPU串行程序,在GPU上运行的并行化程序能实现明显加速,因而具有很好的工程应用价值。     

TinyPBC: Pairings for authenticated identity-based non-interactive key distribution in sensor networks

Key distribution in Wireless Sensor Networks (WSNs) is challenging. Symmetric cryptosystems can perform it efficiently, but they often do not provide a perfect trade-off between resilience and storage. Further, even though conventional public key and elliptic curve cryptosystems are computationally feasible on sensor nodes, protocols based on them are not, as they require the exchange and storage of large keys and certificates, which is expensive.Using Pairing-Based Cryptography (PBC) protocols parties can agree on keys without any interaction. In this work, we (i) show how security in WSNs can be bootstrapped using an authenticated identity-based non-interactive protocol and (ii) present TinyPBC, to our knowledge, the most efficient implementation of PBC primitives for 8, 16 and 32-bit processors commonly found in sensor nodes. TinyPBC is able to compute pairings, the most expensive primitive of PBC, in 1.90 s on ATmega128L, 1.27 s on MSP430 and 0.14 s on PXA27x.     

矩形乘法器的另一结构设计

文章给出了矩形乘法器的另一个结构设计,该设计在计算速度上优于文献[1]的方案而劣于文献[2]的方案,在流水线分级方面则比文献[2]的方案有灵活性。这一实现把大整数乘的数据相关之时间代价降为1个二选一选通器加上3位加法器所需的时间,即把乘法器流水线的节拍时间值降到了该值,从而大大提高了用流水线实现大整数乘的效率。在某些应用中,用矩形乘法器来实现平行四边形乘法器的功能,则可大大降低规模。     

两种因特网服务模型的比较研究

未来的计算机网络将是一种能够提供多种有同服务,以支持多种不同应用需求,有着集成服务（ｉｎｔｅｇｒａｔｅｄ ｓｅｒｖｉｃｅｓ）支持能力的网络．这种网络是通过在统一的分组交换网络上实现各种不同的服务性能保证机制来构造的．针对止目前广泛研究的两种不同因特网服务模型进行比较研究,分析它们各自组成部件的功能入作用,比较两者之间存在的内在联系,从而进一步提出了一种融合两者优点的组合扩展模型,并以此为基础提出了