Bulky rigid substitutions: A route to high electron mobility and high solid-state luminescence efficiency of perylene diimide

In this paper, we report that a kind of perylene diimide derivative with bulky rigid substituents, 1,7-bis(p-tert-butylphenoxy)-N,N′-dicyclohexyl-perylene-3,4,9,10-tetracarboxylic diimide (TBPCHPDI) possesses both high electron mobility (1.8 cm² V⁻¹s⁻¹) and high fluorescence quantum yield (0.32) in the solid state. Through X-ray diffraction (XRD), UV–Vis absorption and fluorescence spectra, and differential scanning calorimetry (DSC) measurements, it is demonstrated that the above phenomenon can be ascribed to the unique crystal structure of TBPCHPDI: due to steric hindrance of bulky rigid substituents, the intermolecular π–π actions are neglectable, providing high luminescence efficiency; in the mean time, the spacing between perylene chromophores is still very short (3.47 Å), which is favorable for the hopping transportation of charge carrier from one molecule to neighboring molecule. Therefore, our finding would help design and synthesize novel organic semiconductive materials with potential applications in electrically pumped lasers which require high emission efficiency when large current density is applied.     

Monte Carlo Analysis of Yield and Performance of a GaAs Flash ADC

Monte Carlo methods are used to analyze yields and performance of GaAs flash ADCs.Due to the nonuniformity of threshold voltage,the DNL and INL of flash ADC will decrease approximately linearly.And the higher the resolution of ADC is,the faster these key nonlinear parameters decrease.When the nonuniformity increases to some degree,the yields of GaAs flash ADCs will decrease exponentially,and the missing code will increase more quickly for the higher resolution ADCs.So,GaAs HBT and HEMT with technology of etching stop will be widely used in high speed and high resolution ADCs.     

一种基于阻变单元特性的阻变存储器修复方案

针对新型阻变存储器(RRAM)工艺良率不高的问题,提出了一种新型的修复解决方案,该方案基于阻变单元的特殊性能,即初始状态为高阻,经过单元初始化操作过程后转变为低阻。利用这样特性的阻变单元作为错误检测位、冗余单元作为修复位,提出了三种不同的组织结构来实现修复操作。三种结构由于主存储器、检验位存储器及冗余存储器的组织方式不同,达到了不同的冗余存储器利用率。最后,通过数学分析可以证明,该方案在利用了较少冗余存储器的条件下,可以将阻变存储器的错误率普遍降低10～30倍,实现了较好的修复效果。     

A numerical integration-based yield estimation method for integrated circuits

A novel integration-based yield estimation method is developed for yield optimization of integrated circuits.This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal,the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation(BCT).In order to reduce the estimation variances of the model parameters of the density function,orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations.The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed.Two yield estimation examples,a fourth-order OTA-C filter and a three-dimensional(3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values.Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases.Therefore,our method is more suitable for parametric yield optimization.     

Statistical Design of the Four-MOSFET Structure

The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor and values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.     

多变量工序能力指数系统模型

工序能力最终决定微电子工艺的质量水平。工序能力指数确定能够有效地确保微电子工艺水平。随着微电子工艺水平的快速发展,工艺趋于复杂化,工艺水平评价需要关注一个以上的特征参数。因此,传统的单变量工序能力指数不能有效综合的分析工序的水平。本论文提出了一个多变量工序能力指数模型系统。这个模型系统包括针对数据满足多变量正态分布的域多变量工序能力指数;针对数据不满足多变量正态分布的因子多变量工序能力指数;以及成品率多变量工序能力指数。最后通过实例分析算验证这些多变量工序能力指数是有效和实用的。     

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults. Part of this work has ever appeared in the proceedings of Asian Test Symposium in 2003. Yu-Chiun Lin received his BS degrees in Electrical Engineering from National Central University in 2000, and MS degree from Electrical Engineering of National Tsing Hua University in 2002. Since then, he has been with Ali Corporation as a design engineer. His current interests include the design of USB controllers and imaging periperals. Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the System-On-Chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999, where he is currently an Associate Professor. Dr. Huang’s research interests include CMOS image sensor design, low-power memory design, power estimation, and fault diagnosis methodologies.     

Ultrathin Highly Luminescent Two‐Monolayer Colloidal CdSe Nanoplatelets

Surface effects in atomically flat colloidal CdSe nanoplatelets (NLPs) are significantly and increasingly important with their thickness being reduced to subnanometer level, generating strong surface related deep trap photoluminescence emission alongside the bandedge emission. Herein, colloidal synthesis of highly luminescent two‐monolayer (2ML) CdSe NPLs and a systematic investigation of carrier dynamics in these NPLs exhibiting broad photoluminescence emission covering the visible region with quantum yields reaching 90% in solution and 85% in a polymer matrix is shown. The astonishingly efficient Stokes‐shifted broadband photoluminescence (PL) emission with a lifetime of ≈100 ns and the extremely short PL lifetime of around 0.16 ns at the bandedge signify the participation of radiative midgap surface centers in the recombination process associated with the underpassivated Se sites. Also, a proof‐of‐concept hybrid LED employing 2ML CdSe NPLs is developed as color converters, which exhibits luminous efficacy reaching 300 lm W_opt^?1. The intrinsic absorption of the 2ML CdSe NPLs (≈2.15 × 10⁶ cm^?1) reported in this study is significantly larger than that of CdSe quantum dots (≈2.8 × 10⁵ cm^?1) at their first exciton signifying the presence of giant oscillator strength and hence making them favorable candidates for next‐generation light‐emitting and light‐harvesting applications.     

Photon-assisted capacitance–voltage study of organic metal–insulator–semiconductor capacitors

The results are reported of a detailed investigation into the photoinduced changes that occur in the capacitance–voltage (C–V) response of an organic metal–insulator–semiconductor (MIS) capacitor based on the organic semiconductor poly(3-hexylthiophene), P3HT. During the forward voltage sweep, the device is driven into deep depletion but stabilizes at a voltage-independent minimum capacitance, C_min, whose value depends on photon energy, light intensity and voltage ramp rate. On reversing the voltage sweep, strong hysteresis is observed owing to a positive shift in the flatband voltage, V_FB, of the device. A theoretical quasi-static model is developed in which it is assumed that electrons photogenerated in the semiconductor depletion region escape geminate recombination following the Onsager model. These electrons then drift to the P3HT/insulator interface where they become deeply trapped thus effecting a positive shift in V_FB. By choosing appropriate values for the only disposable parameter in the model, an excellent fit is obtained to the experimental C_min, from which we extract values for the zero-field quantum yield of photoelectrons in P3HT that are of similar magnitude, 10^?5 to 10^?3, to those previously deduced for π-conjugated polymers from photoconduction measurements. From the observed hysteresis we deduce that the interfacial electron trap density probably exceeds 10¹⁶ m^?2. Evidence is presented suggesting that the ratio of free to trapped electrons at the interface depends on the insulator used for fabricating the device.