Leech格的限界距离译码

本文利用将Ｌｅｅｃｈ格投影于ＧＦ（４）得到（６，３，４）Ｈｅｘａｃｏｄｅｘ这一性质，提出一种新的Ｌｅｅｃｈ格的限界距离译码算法，复杂度为最多１１５１次，最少５７５次，平均９１１次实数运算，而目前已知最快的ＢＤ译码算法复杂度为最多１００７次，最少９１１次运算，平均９５３次，新算法在平均和最少复杂度方面有所降低，计算机模拟表明新算法相对于最在似然译码仅有０．０２ｄＢ的编码增益损失，而文献（１０）中算法     

环焊缝强度匹配对长输管道性能的影响

环焊缝强度匹配是天然气管道研究与应用的热点问题.介绍了焊接接头匹配性的概念,阐述了不等强匹配对长输管道极限载荷、韧性、残余应力、缺陷容限等的影响,最后提出了在长输管道环焊缝强度匹配领域需要解决的技术问题.     

加氢换热器制造质量控制

加氢换热器是加氢装置关键设备之一,制造过程中质量控制不容忽视,焊接缺陷是最常见的。重大设备制造按要求委托第三方进行监理,设备监理对缺陷的判断处理非常重要。灵活应用各种质量控制工具,分析判断质量缺陷原因,达到控制质量目的。     

Highly Efficient Rapid Annealing of Thin Polar Polymer Film Ferroelectric Devices at Sub‐Glass Transition Temperature

An unexpected rapid anneal of electrically active defects in an ultrathin (15.5 nm) polar polyimide film at and below glass transition temperature (T_g) is reported. The polar polymer is the gate dielectric of a thin‐film‐transistor. Gate leakage current density (J_g) through the polymer initially increases with temperature, as expected, but decreases rapidly at T_g ? 60 °C. After ≈2 min at T_g, the leakage is reduced by nearly three orders of magnitude. A concomitant observation is that the drain current (I_d)–gate voltage (V_g) hysteresis decreases with temperature, reaching zero at nearly the same temperature at which J_g collapses. As J_g drops further, the drain current hysteresis increases again but in the opposite direction. This combination strongly supports the interpretation of rapid defect annealing.     

Al-Ni-Rh复杂合金相中特殊面缺陷的电子显微学研究

利用高分辨透射电子显微学方法,研究了复杂合金相ξ'-Al-Ni-Rh和ξ-Al-Ni-Rh相中一种特殊类型面缺陷.这种面缺陷的晶体学特点是,其结构特征不仅涉及描述通常晶体中面缺陷的平移矢量,而且还涉及原子团簇之间的位置交换.而后者通常出现在不具平移周期性的准晶中,称为相子缺陷.研究表明,这种特殊的面缺陷不仅呈现随机分布状态,也可周期性排列形成新的大晶胞调制结构.此外,本文还将报道与这种特殊面缺陷相关的晶界、畴界、孪晶、层错等面缺陷的研究.     

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits

In this paper, we present an exhaustive study on the influence of resistive-open defects in pre-charge circuits of SRAM memories. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. We have analyzed the impact of resistive-opens placed in different locations of these circuits. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled by Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more effective in terms of resistive defect detection than that of URRFs and we list the necessary test conditions to detect them.

基于Schur运算格的线性ICA估计算法

从几何角度来看,线性ICA(Independent Component Analysis)估计可以通过角度变换来实现.因此,本文提出一种新颖的,基于Schur运算格的格型ICA估计算法,格型算法较之其它算法稳定,易于扩展,易于硬件软件实现.仿真结果表明,该算法性能令人满意.     

Fe-B合金激光熔凝形成非晶态机理探讨

本文对激光表面熔区的显微组织进行了热力学和动力分析，提出一个简化的熔池中温度分布的物理模型，分析了非晶态形成过程。用ＣＷＣＯ２激光扫描Ｆｅ—Ｂ合金表面，得到１３０μｍ～２００μｍ厚度的非晶层，并对激光低速扫描时熔区再结晶点阵常数变化的有关数据进行了对比，对激光非晶态形成的条件及有关工艺参数进行了分析和讨论。     

Removal of threading dislocations from patterned heteroepitaxial semiconductors by glide to sidewalls

We have shown that threading dislocations can be removed from patterned heteroepitaxial semiconductors by glide to the sidewalls, which is driven by the presence of image forces. In principle, it should be possible to attain highly mismatched heteroepitaxial semiconductors which are completely free from threading dislocations, even though they are not pseudomorphic, by patterned heteroepitaxial processing. There are two basic approaches to patterned heteroepitaxial processing. The first involves selective area growth on a pre-patterned substrate. The second approach involves post-growth patterning followed by annealing. We have developed a quantitative model which predicts that there is a maximum lateral dimension for complete removal of threading dislocations by patterned heteroepitaxy. According to our model, this maximum lateral dimension is proportional to the layer thickness and increases monotonically with the lattice mismatch. For heteroepitaxial materials with greater than 1% lattice mismatch, our model predicts that practical device-sized threading dislocation-free regions may be realized by patterned heteroepitaxial processing.     

Progress in CdZnTe substrate producibility and critical drivers of IRFPA yield originating with CdZnTe substrates

With the goal of maximizing the yield of infrared focal plane arrays (IRFPAs), Santa Barbara Research Center’s (SBRC) Infrared Materials Producibility Program (IRMP) has focused on assessing and improving the quality, yield, and throughput of CdZnTe substrates. A baseline detector lot was fabricated to identify the critical drivers of IRFPA yield coming from the substrates and to evaluate the quality and yield of the current vendor base for CdZnTe substrates. Substrate induced defects and impurities that can potentially affect device performance and operability were carefully mapped out in detail on 44 × 67 mm² size substrates, received from IRMP substrate vendors as well as SBRC. This paper will report on the correlations found between this substrate characterization data base and the IRFPA level defect distributions. Key results from these correlation studies are: (1) extended defects found on the substrates with the Nakagawa etch correlated well with responsivity reduction in the final IRFPA; (2) cross-hatch patterns that were evident in the responsivity map correlated well with similar features seen by x-ray topography on LPE double layers; and (3) a possible correlation of device performance (leakage current at 78K) with copper and lithium impurities in the substrate. Recent initiatives toward improving the quality and yield of the substrate growth process have focused on improving purity in the pre-growth charge preparation, modification of growth parameters to reduce defects and scaling up of the vertical Bridgman growth process from its current 67 mm diameter boule size to 92 mm diameter boules. Promising initial results from the large diameter boule growth process will be shown. The 92 mm diameter CdZnTe boule (6 kg charge) shows two predominant single crystal grains encompassing 75% of boule volume. Defect characterization of boules grown under baseline and modified conditions is discussed.