Known Good Die

Advances in reducing size and increasing functionality of electronics have been due primarily to the shrinking geometries and increasing performance of integrated circuit technologies. Recently, development efforts aimed at reducing size and increasingfunctionality have focused on the first level of the electronicpackage. The result has been the development of multichip packaging,technologies in which bare IC chips are mounted on a single high density substrate that serves to package thechips, as well as interconnect them. A number of benefits accruebecause of multichip packaging, namely, increased chip density,space savings, higher performance, and less weight. Therefore, thesetechnologies are attractive for today's light weight, portable, highperformance electronic equipment and devices.In spite of these benefits, multichip packaging has not shown the kind of explosive growth and expansion that was predicted[1]. A major inhibitor for these technologies has been theavailability of fully tested and conditioned bare die, orknown good die. This paper reviews the issues and technologies associated with test and burn-in of bareor minimally packaged IC products.     

测控电路设计中运算放大器的若干误用

运算放大器(运放)在测控电路中有重要而广泛的应用,已成为测控电路中的基本器件.测控电路的特点对运放的应用设计有更高的要求.在测控电路设计中,往往因运放的应用设计不当或错误而降低电路的性能,甚至电路不能正常工作.总结了在测控电路设计中运放的几种重要误用,分析了其原因,并给出了相应的对策.相关的讨论与结论对运放在测控电路中的应用设计具有参考作用.     

一种PL/SQL程序包失效的解决方案

针对pl/sql程序包在运行中有时会出现＂程序包失效＂的异常情况,通过深入分析该错误与对象依赖机制、自动重编机制和程序包运行机制的关系,结合3个不同的实验,证实了该错误与程序包中全局变量/常量的独有特性有关,并提供了一种解决方案：对新开发程序包,应尽量避免使用全局变量,使用函数来代替全局常量;对现有程序包,在逐步实施代码改造同时,应密切监控错误的发生、定期检测失效的程序包并自动进行重新编译处理。     

封装技术评述

评述了当前封装技术的特点以及应用,介绍了多芯片组件、突点互连技术、球栅阵列、板上芯片、板上倒装芯片和柔性电路板上芯片技术以及片上引线与引线上芯片技术。     

半导体封装中的可视化技术

树脂传递模封装是广泛使用的可靠性量产性均好的半导体封装方法。但随着封装体（PACKAGE）尺寸的日益薄型化和多腿化,不可避免地会发生与树脂在模腔中流动状态有关的空隙等使制品失效的不良模式。这样,通过观察树脂流动状态及对空隙的分布进行研究,对于研究空隙发生机理从而抑制空隙发生具有重要意义。本文将着重介绍两种新的研究实验方法：（1）应用玻璃嵌入式新型可视化模具观察树脂在模腔中的流动状态;（2）采用超声波探查图像装置（简称SAT）进行树脂封装体内部的观察。     

Microstructures and degradation of heat sink very-thin quad flat package no-leads Pb-free Sn-Ag-Cu solder joints after thermal aging

Heat sink very-thin quad flat package no-leads (HVQFN) packages soldered with Sn-3.8Ag-0.7Cu on metallized laminate substrates have been put to thermal aging. Temperatures from 140°C to 200°C for times up to 30 weeks were applied. The solder joint microstructure develops intermetallic compound layers and voids within the solder. Due to this, the mechanical reliability of the HVQFN inner lead solder joints is degraded. The intermetallic layers are of the type (Cu, Y)₆Sn₅, with Y=Ni, Au or Ni+Au, as well as Cu₃Sn, and follow a power law with aging time: X=C·tⁿ, where n=0.4 to 1.9 depending on temperature. The voids within the solder are attributed to Sn depletion of the solder in favor of the growth of (Cu,Ni)₆Sn₅. They are more pronounced the less the solder volume is in proportion to the intermetallic diffusion area. The amount of voids is quantified as a percentage of the residual solder. The time to reach the failure criterion of 50%, i.e., t_50%, is related to the absolute temperature according to an Arrhenius equation with an activation energy E_a=0.95 eV. This equation is used for determination of the maximum allowable temperature at a certain required operating lifetime.     

硫系玻璃的粘弹性及模压工艺的仿真

为了对红外玻璃的精密模压工艺进行仿真分析,利用热机械分析方法,对红外玻璃在高温下的粘弹性进行了研究。利用热机械分析仪观察玻璃在高温下的蠕变响应,对所获得的蠕变数据进行重新计算和整理,拟合获得了所需的PRONY级数的参数,并将其输入ANSYS软件,进行模压仿真。实验结果表明,玻璃在高温下会呈现出典型的粘弹性属性,其弹性模量在较长的时间后会下降5个数量级。选择微米结构进行仿真的结果表明,当模压时间超过13 min后,时间对模具腔体的填充率的影响不大。仿真分析还发现,温度和压力的大小对模压工艺的填充率有明显影响。     

集成化DAM变频电路设计

介绍了数字阵列雷达中DAM（数字阵列模块）内部的高度集成化的变频电路的设计思想,用于数字阵列雷达的收发变频通道,各项指标均满足系统要求,可达到常规分立元件电路的指标,讲述了采用MCM（多芯片组件）技术,结合电路优化集成设计,将有源变频器芯片、开关等器件集成于金属陶瓷结构的封装内,使得DAM的变频通道集成度得以大幅度提高。     

多波长集成光源阵列封装用微波馈线设计

针对多波长集成光源阵列封装设计了一种具有低传输损耗、低串扰的阵列微波馈线。通过分析微带线和接地共面波导在传输高频微波信号时的优缺点,设计了一种桥型微波馈线结构。同时利用有限元法,对馈线尺寸参数进行仿真优化。在30GHz范围内,得到了反射系数低于-17dB、传输损耗小于0.4dB、相邻信号电极间串扰小于-26dB的仿真结果。设计了基于金线键合的阵列芯片方案,并通过有限元法仿真确定了传输性能良好的封装间距。     

倒装晶片装配工艺及其对表面贴装设备的要求

随着市场对于电子产品特别是消费型电子产品持续要求越来越高,要求其短小轻薄、功能高度集成、价格更加便宜、储空间更大,元件的小型化高密度封装形式越来越多,如多模块封装（MCM）、系统封装（SiP）、倒装晶片（FC）等应用得越来越多。这些技术的出现更加模糊了一级封装与二级装配之间的界线,勿庸置否,随着小型化高密度封装的出现,对高速与高精度装配的要求变得更加关键。相关的组装设备和工艺也更具先进性与高灵活性。由于倒装晶片比BGA或CSP具有更小的外形尺寸,更小的球径和球间距,它对植球工艺、基板技术、材料的兼容性、制造工艺以及检查设备和方法提出了前所未有的挑战。