一种大动态范围扫描变你的电子光学结构

提出并设计了一种旨在获得大的动态范围的扫描变像管的电子光学结构，用数值方法给出了有关电子光学设计参数，如时间、空间响应特性。该管型在保证大的阴极具有大的有效使用面积的情况下，极大地减小了光电子的渡越时间。由此减小空间电荷效应对扫描变像管性能的影响，从而改善扫描变像管的动态范围。通过对光电子在该系统内传输的模拟计算，得到脉冲半宽在0．5ps以上的脉冲的动态范围约在200的估算结果。     

The microstructure of Cu films deposited by the self-ion assisted technique

The microstructures of Cu films deposited by the self-ion assisted, partially ionized beam (PIB) deposition technique under two different accelerating potentials, 0 KeV and 6 KeV, are compared. The 6 KeV film shows a bimodal (111) fiber and (100) fiber texture with an abundance of twin boundaries and a relatively large average grain size with a typical lognormal distribution. The 0 KeV film consists of small, mostly (111) oriented grains with islands of abnormally large (100) grains. The controlling factors for the abnormal growth of the (100) grains are discussed in relation to the observed microstructures, showing that all factors necessary for abnormal (100) growth are present in the films.     

Intermetallic compounds formed at the interface between liquid indium and copper substrates

The interfacial reactions between liquid In and Cu substrates at temperatures ranging from 175°C to 400°C are investigated for the applications in bonding recycled sputtering targets to their backing plates. Experimental results show that a scallop-shaped Cu₁₆In₉ intermetallic compound is found at the Cu/In interface after solder reactions at temperatures above 300°C. A double-layer structure of intermetallic compounds containing scallop-shaped Cu₁₁In₉ and continuous CuIn is observed after the Cu/In interfacial reaction at temperatures below 300°C. The growth of all these intermetallic compounds follows the parabolic law, which implies that the growth is diffusion-controlled. The activation energies for the growth of Cu₁₆In₉, Cu₁₁In₉, and CuIn intermetallic compounds calculated from the Arrhenius plot of growth reaction constants are 59.5, 16.9, and 23.5 kJ/mole, respectively.     

High Hall Mobility P‐type Cu2SnS3‐Ga2O3 with a High Work Function

A new transparent p‐type oxide semiconductor (POS) is reported, Cu₂SnS₃‐Ga₂O₃, having high Hall mobility of 36.22 cm² V⁻¹s⁻¹, and high work function of 5.17 eV. The existence of Cu₂SnS₃ and Ga₂O₃ phases in the film is confirmed by X‐ray photoelectron spectroscopy results and the Cu₂SnS₃ shows polycrystalline structure according to Raman spectrum and X‐ray diffraction analysis. The transparent Cu₂SnS₃‐Ga₂O₃ exhibits the carrier concentration of 5.86 × 10¹⁶ cm⁻³, and electrical resistivity of 1.94 Ω·cm. The transparent POS is applied to green quantum light‐emitting diodes (QLEDs) as a hole injection layer (HIL) because of its high work function. The QLED exhibits the maximum current efficiency of 51.72 cd A⁻¹, power efficiency of 31.97 lm W⁻¹, and external quantum efficiency (EQE) of 14.93%, which are much higher than the QLED using polyethylene dioxythophene:poly(styrenesulfonate) HIL exhibiting current efficiency of 42.66 cd A⁻¹, power efficiency of 20.33 lm W⁻¹, and EQE of 12.36%. The Cu₂SnS₃‐Ga₂O₃ developed in this work can be widely used as a transparent and conductive p‐type oxide for thin‐film devices.     

用于相变存储器的W亚微米管加热电极性能

为了降低C-RAM器件的操作电流,利用0.18μm标准CMOS工艺线制备出外径为260nm的W亚微米管加热电极,并对其进行了电学性能的表征.使用W亚微米管加热电极制备出C-RAM器件,并通过疲劳特性测试分析了器件失效的原因.结果表明,W亚微米管具有良好的电学稳定性和疲劳特性,为降低C-RAM器件的操作电流提供了一种非常有效的途径.     

Texture investigation of copper interconnects with a different line width

To understand the effect of line width on textural and microstructural evolution of Cu damascene interconnect, three Cu interconnects samples with different line widths are investigated. According to x-ray diffraction (XRD) results, the (111) texture is developed in all investigated lines. Scattered {111}〈112〉 and {111}〈110〉 texture components are present in 0.18-μm-width interconnect lines, and the {111}〈110〉 texture was developed in 2-μm-width interconnect lines. The directional changes of the (111) plane orientation with increased line width were investigated by XRD. In addition, microstructure and grain-boundary character distribution (GBCD) of Cu interconnect were measured using electron backscattered diffraction (EBSD) techniques. This measurement demonstrated that a bamboo-like microstructure is developed in the narrow line, and a polygranular structure is developed in the wider line. The fraction of ∑3 boundaries is increased as the line width increases but is decreased in the blanket film. A new interpretation of textural evolution in damascene interconnect lines after annealing is suggested, based on the state of stress and growth mechanisms of Cu deposits.     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

Enhancement of adhesion strength of Cu layer with low dielectric constant SiC:H liners in Cu interconnects

One of the primary candidates for the liner/etch stop layer in damascene process is silicon nitride (Si₃N₄). However, silicon nitride has a high dielectric constant of 7.0. To reduce the effective dielectric constant in Copper (Cu) damascene structure, dielectric SiC:H (prepared by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane source) as the Cu diffusion barrier was studied. The dielectric constant of SiC:H used is 4.2. A systematic study was made on the properties of liner material and electro-chemically plated (ECP) Cu to enhance the adhesion strength in Cu/low-dielectric constant (k) multilevel interconnects. Though the effects of as Si₃N₄ the liner have been much studied in the past, less is known about the relation between adhesion strength of ECP Cu layer and physical vapor deposited (PVD) Cu seeds, with seed thickness below 1000 Å. The annealing of Cu seed layer was carried out at 200 °C in N₂ ambient for 30 min was carried out to study the impact on adhesion strength and the microstructure evolution on the adhesion between ECP Cu and its barrier layer. In the study, our claim that SiC:H barrier/etch stop layer is essential for replacing conventional Si₃N₄ layer in enhancing adhesion strength and interfacial bonding between Cu/dielectric interconnects.     

Low-cycle fatigue behavior of Sn-Ag, Sn-Ag-Cu, and Sn-Ag-Cu-Bi lead-free solders

Low-cycle fatigue (LCF) tests on as-cast Sn-3.5Ag, Sn-3Ag-0.5Cu, Sn-3Ag-0.5Cu-1Bi, and Sn-3Ag-0.5Cu-3Bi solders was carried out using a noncontact strain-controlled system at 20°C with a constant frequency of 0.1 Hz. The addition of Cu does not significantly affect the fatigue life of eutectic Sn-Ag solder. However, the fatigue life was significantly reduced with the addition of Bi. The LCF behavior of all solders followed the Coffin-Manson relationship. The fatigue life of the present solders is dominated by the fracture ductility and can be described by the ductility-modified Coffin-Manson’s relationship. Steps at the boundaries of dendrite phases were the initiation sites for microcracks for Sn-3.5Ag, Sn-3Ag-0.5Cu, and Sn-3Ag-0.5Cu-1Bi solders, while for Sn-3Ag-0.5Cu-3Bi solder, cracks initiated along both the dendrite boundaries and subgrain boundaries in the dendrite phases. The linking of these cracks and the propagation of cracks inside the specimen occurred both transgranularly through eutectic phases and intergranularly along dendrite boundaries or subgrain boundaries.     

毫米波耦合腔行波管高频系统的基本特点与工艺结构综述

根据国外有关文献资料并结合工作实践,对毫米波耦合腔行波管高频系统的基本特点以及有关的工艺结构问题进行邀请赛,可供从事这方面研究工作的人员参考。