纳米MOSFET寄生电阻模型分析

随着器件尺寸的缩小,寄生电阻对器件性能的影响不可忽视,为准确预测器件的寄生电阻并了解器件参数对寄生电阻的影响,需要有准确的寄生电阻模型。该文分析了短沟道寄生电阻模型,研究了短沟道寄生电阻模型在栅压较小时与模拟结果存在较大误差的原因,并对模型进行了改进。最后分析了器件参数对寄生电阻的影响,提出未来减小寄生电阻需要和可能采取的措施。     

轨道交通站台安全门控制系统

轨道交通站台安全门作为公共安全防护设备,广泛应用在地铁、轻轨等轨道交通中的高架和地面站台上,具有节能、环保和安全功能。因此它在设计、制造、安装过程中需要充分考虑其自身的可靠性及乘客安全、行车安全。本文将对安全门系统的网络、控制及软件三方面进行详细论述。     

中国传统建筑门的形态研究

中国古建筑的门,不仅仅只是一种建筑形态,而且是人们心目中的一个重要概念。因为概念与原型之间的互动,在有关门的具体的建筑活动中,这些形而上的观念又不断显露并发展,促进着门本身在艺术上的进步。文章从文化和心理方面等多方面对中国古建筑的门进行了分析研究。     

SOPC外扩SDRAM的设计要点分析

针对SDRAM正常工作所需要的条件较为严格,介绍将SDRAM接入SOPC的设计方法及要点。重点介绍在PCB设计阶段所要注意要点,以及根据不同的FPGA和SDRAM来选择时钟频率,最后详细介绍如何计算锁相环的相移,使得输出的SDRAM时钟和控制器时钟同步以确保SDRAM正常工作。     

When do extra majority gates help? Polylog (N) majority gates are equivalent to one

Suppose that a Boolean functionf is computed by a constant depth circuit with 2 ^m AND-, OR-, and NOT-gates—andm majority-gates. We prove thatf is computed by a constant depth circuit with AND-, OR-, and NOT-gates—and a single majority-gate, which is at the root.One consequence is that if a Boolean functionf is computed by an AC⁰ circuit plus polylog majority-gates, thenf is computed by a probabilistic perceptron having polylog order. Another consequence is that iff agrees with the parity function on three-fourths of all inputs, thenf cannot be computed by a constant depth circuit with AND-, OR-, and NOT-gates, and majority-gates.     

A variable-precision square root implementation for field programmable gate arrays

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.Notation S_j square root digit of weight 2^–j - S _j {–1, 0, 1} - S[j] computed square root value as of stepj - S _j ^s sign bit in the representation ofS _j in sign and magnitude form - S _j ^m magnitude bit in the representation ofS _j in sign and magnitude form - w[j] residual at stepj in two's complement carry-save representation - a sum vector in the carry-save representation of 2w[j] - b carry vector in the carry-save representation of 2w[j] - a _i bit of weight 2^–i in the sum vector,a - b_i bit of weight 2^–i in the carry vector,b - T[j]=–S[j – 1]s_j – s _j ² 2^–(j+1) T _i bit of weight 2^–i inT     

浮动电极对屏蔽栅沟槽型MOSFET特性的影响

提出了在屏蔽栅沟槽型MOSFET(SGT)的沟槽侧壁氧化层中形成浮动电极的结构,通过改善电场分布,优化了特征导通电阻与特征栅漏电容。在传统SGT结构的基础上,仅通过增大外延层掺杂浓度,改变浮动电极的长度和位置以及氧化层厚度,最终得到击穿电压为141.1 V、特征导通电阻为55 mΩ·mm²、特征栅漏电容为4.72 pF·mm^-2的浮动电极结构。与相同结构参数的SGT结构相比,在击穿电压不变的条件下,浮动电极结构的特征导通电阻降低了9.3%,Baliga优值提升了13%,特征栅漏电容降低了28.4%。     

Ultraviolet photodetectors and readout based on a-IGZO semiconductor technology

In this work, real-time ultraviolet photodetectors are realized through metal–semiconductor–metal (MSM) structures. Amorphous indium gallium zinc oxide (a-IGZO) is used as semiconductor material and gold as metal electrodes. The readout of an individual sensor is implemented by a transimpedance amplifier (TIA) consisting of an all-enhancement a-IGZO thin-film transistor (TFT) operational amplifier and a switched capacitor (SC) as feedback resistance. The photosensor and the transimpedance amplifier are both manufactured on glass substrates. The measured photosensor possesses a high responsivity R , a low response time t _{R E S} , and a good noise equivalent power value NEP .     

基于Attention-CGRU网络的中文语音情感识别

正确识别语音中包含的情感信息可以大幅提高人机交互的效率.目前,语音情感识别系统主要由语音特征抽取和语音特征分类两步组成.为了提高语音情感识别准确率,选用语谱图而非传统声学特征作为模型输入,采用基于attention机制的CGRU网络提取语谱图中包含的频域信息和时域信息.实验结果表明:在模型中引入注意力机制有利于减少冗余信息的干扰,并且相较于基于LSTM网络的模型,采用GRU网络的模型预测精确度更高,且在训练时收敛更快,与基于LSTM的基线模型相比,基于GRU网络的模型训练时长只有前者的60%.     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.