Solid-state annealing behavior of two high-Pb solders, 95Pb5Sn and 90Pb10Sn,on Cu under bump metallurgy

The solid-state annealing behavior of two high-lead solders, 95Pb5Sn and 90Pb10Sn (in wt.%), was examined. After reflow, Cu₃Sn intermetallics formed on the Cu under bump metallurgy (UBM) for both solder alloys. However, solidstate annealing produced significantly different reaction morphologies for the two solder compositions. The Cu₃Sn intermetallics spalled off faster at higher temperatures in the 95Pb5Sn solder. In the case of 90Pb10Sn solder, the Cu₃Sn intermetallics continued to grow even after 1500 h at 170°C. The difference was explained by a two-step phenomenon—Sn diffusion from the bulk solder region to the solder/Cu₃Sn interface (J_Sn), and subsequent intermetallic formation (I_Cu3Sn) by interdiffusion of Cu and Sn. For 95Pb5Sn, the relation, J_Sn < I_Cu3Sn was postulated because of insufficient supply of Sn. The relation, J_Sn > I_Cu3Sn was suggested for the continuous intermetallic growth of the 90Pb10Sn solder. Although a small difference was expected between the two quantities in both solder alloys, the difference in the solid-state annealing behavior was dramatic.     

喷镀系统在凸点制备中的应用

介绍了利用电镀法制造晶圆凸点的典型工艺和喷镀设备.喷镀系统是凸点电镀设备中最关健的部件.通过计算机软件模拟试验,对喷镀系统中的喷杯体和匀流板等各种参数和位置进行了优化设计,并在设备上应用验证.该系统在凸点电镀设备上应用后,在晶圆片上成功做出了高质量的均匀凸点,取得了良好效果.     

Effect of substrate metallization on interfacial reactions and reliability of Sn-Zn-Bi solder joints

The scope of this paper covers a comprehensive study of the lead-free Sn-Zn-Bi solder system, on Cu, electrolytic Ni/Au and electroless Ni(P)/Au surface finishes. This includes a study of the shear properties, intermetallic compounds at the substrate-ball interface and dissolution of the under bump metallization. The Sn-8Zn-3Bi (wt.%) solder/Cu system exhibited a low shear load with thick IMCs formation at the interface. The dissolution of the Cu layer in the Sn-Zn-3Bi solder is higher than that of the other two Ni metallizations. It was found that the formation of a thick Ni-Zn intermetallic compound (IMC) layer at the solder interface of the electrolytic Ni bond pad reduced the mechanical strength of the joints during high temperature long time liquid state annealing. The solder ball shear-load for the Ni(P) system during extended reflow increased with an increase of reflow time. No spalling was noticed at the interface of the Sn-Zn-3Bi solder/Ni(P) system. Sn-8Zn-3Bi solder with electroless Ni(P) metallization appeared as a good combination in soldering technology.     

倒装芯片凸焊点的UBM

介绍了倒装芯片凸焊点的焊点下金属（UBM）系统,讨论了电镀Au凸焊点用UBM的溅射工艺和相应靶材、溅射气氛的选择,给出了凸焊点UBM质量的考核试验方法和相关指标。     

金凸点键合工艺在国产陶瓷外壳中的应用

国产陶瓷外壳已经逐渐应用于高可靠要求的各类电子元器件的封装上。在IC封装过程中, 随着封装密度的提高,因其键合指状引线的质量难以满足键合工艺要求,为使其能达到工艺控制要求, 我们开发出一些相应的封装技术,提高了产品的可靠性。金凸点键合工艺用于提高国产陶瓷外壳键合指 上的键合引线强度有非常明显的效果,是一项较新的技术。     

凸点下金属层湿法刻蚀与凸点底切的控制

介绍了电镀凸点封装工艺流程和其中有关金属层湿化学刻蚀的问题.通过槽式批量和单片机刻蚀相应的UBM(凸点下金属层)的均匀度、刻蚀速率和凸点底切的对比,结果显示单片湿法刻蚀机刻蚀均匀度小于5%且片与片之间刻蚀速率差异小于2%,以及凸点底切小于2μm.槽式刻蚀均匀度较差,一般会大于20%,同时同一批次片与片之间刻蚀速率差异也较大,实验显示超过10%,且刻蚀后凸点底切较深.因此采用单片机进行UBM金属刻蚀可以较好的控制刻蚀过程和提高产品的良率.     

凸点晶圆测试共性问题研究与应用

集成电路"轻、薄、小"的趋势使新封装技术在产业中不断得以应用。晶圆凸点工艺作为新封装技术的关键工序尤为重要,相应的凸点晶圆测试方案是产业面临的现实问题。针对凸点晶圆测试中出现的新问题和技术难点,结合在多个凸点晶圆测试开发和量产过程中积累的成功经验,按照晶圆测试控制流程,依次阐述在凸点晶圆测试中碰到的共性问题,如针对凸点晶圆测试的新型探针卡及测试过程中针压控制、凸点损伤与量产测试中关键操作控制、在线清针与检查、工艺数据测试衔接等。并提供预防凸点损伤的过冲控制参数自动获取解决方案和凸点晶圆并行测试解决方案,实现凸点晶圆可靠的量产测试,有效提高了凸点晶圆的测试能力。     

Study of Fracture Mechanics in Testing Interfacial Fracture of Solder Joints

This paper is concerned with the mechanics of interfacial fracture that are active in two common testing configurations of solder joint reliability. Utilizing eutectic Pb-Sn/Cu as a reference system and assuming the presence of a predefined crack size in the intermetallic compound (IMC) layer, stress intensity factors (K _I and K _II) at the crack are numerically calculated for the two given configurations. The analysis of the tensile test configuration reveals that the fracture occurs by the crack-opening mode (K _I mode), as anticipated, but that it is greatly assisted by the viscoplasticity of the solder. With nonuniform viscoplastic deformation across the joint, K _I is found to increase much more rapidly than it would without the solder, decreasing the critical crack size to the micron scale. The same mechanism is also responsible for the development of a K _II comparable to K _I at the crack tip, that is, |K _I /K _II| ~ 1. It is also found that the predominant fracture mode in the bump shear configuration is crack opening, not crack shearing. This is an unexpected result, but numerical analyses as well as experimental observations provide consistent indications that fracture occurs by crack opening. During shear testing, bump rotation due to nonzero rotational moment in the test configuration is found to be responsible for the change in the fracture mode because the rotation makes K _I become dominant over K _II. With rotational moment being affected by the geometry of the bump, it is further found that the fracture behavior may vary with bump size or shape.     

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.     

一种CMOS驱动器的晶圆级芯片尺寸封装

采用晶圆级芯片尺寸封装(WLCSP)工艺完成了一款小型化CMOS驱动器芯片的封装.此WLCSP驱动器由两层聚酰亚胺(PI)层、重分配布线层、下金属层和金属凸点等部分构成.完成了WLCSP驱动器的设计,加工和电性能测试,并且对其进行了温度冲击、振动和剪切力测试等可靠性试验.结果表明,经过晶圆级封装的CMOS驱动器体积为1.8mm×1.2mm×0.35 mm,脉冲上升沿为2.3 ns,下降沿为2.5ns,开关时间为10.6 ns.将WLCSP的驱动器安装至厚度为l mm的FR4基板上,对其进行温度冲击试验及振动试验后,凸点正常无裂痕.无下填充胶时剪切力为20 N,存在下填充胶时,剪切力为200 N.