环江油田巴19区块长7段钙夹层评价与大斜度井分段压裂优化

为实现最大化油藏接触,提高油藏产出水平,长庆环江油田巴19区块长7油藏采用大斜度井开发方式。在初期压裂改造中,由于忽视了层内钙质夹层对压裂缝高的影响,导致实际裂缝的几何形态与设计产生巨大偏差,出现了邻井裂缝串通及生产高含水等问题。本文通过研究油藏剖面测井特征,在细分层位基础上分析纵向应力分布,研究“复合层效应”影响裂缝缝高延伸的关键因素,优化了分段压裂方案,获得了更好的水力裂缝几何形态和尺寸。技术调整后现场压裂工艺质量获得提高,长7段油藏压裂改造质量优良率100%,大大提高了该区块的开发水平。     

Coating of TiB2 dispersed Ti50Ni50 superelastic alloy layer onto Ti-6Al-4V alloy by spark and resistance sintering

The spark and resistance sintering (SRS) of a mixture of Ti, Ni, and TiB₂ powders was carried out to form a TiB₂ dispersed TiNi alloy layer onto a Ti-6Al-4V alloy substrate. The strength and delamination resistance of the surface layer were evaluated by three-point bending tests. The results showed that the bending strength of the specimen with the TiNi alloy surface layer without TiB₂ particles sintered at 1273 K was low because the crack initiation occurred at an early stage of loading in a thick interface layer containing brittle Ti-Ti₂Ni eutectic. By decreasing the sintering temperature to 1200 K, the bending strength increased and the crack initiation occurred from the surface because the interface layer was thin and did not contain the brittle Ti-Ti₂Ni eutectic. For the specimens with TiB₂ dispersed TiNi surface layer that was sintered at 1273 K, the bending strength was larger than that of the specimens with TiNi surface layer because the interface layer does not contain the Ti-Ti₂Ni eutectic and compressive residual stress generated in the surface layer during cooling process after SRS suppresses the crack initiation on the surface. The coating of TiB₂ dispersed TiNi alloy onto titanium alloys by SRS provides strong interface to prevent delamination of the surface layer, strong surface due to residual compressive stress, and wear-resistant surface due to the existence of hard TiB₂ particles and superelastic deformation of TiNi matrix.     

Experimental study of CT test on the failure of acrylate spray-applied waterproof layer in the groundwater environment

In this study the computerized tomography (CT) was first used to quantitatively analyze the failure of acrylate spray-applied waterproof membrane in the groundwater environment. The results of the CT tests show that it is feasible to use the CT to quantitatively analyze the failure of the waterproof membrane and the CT method has the advantages of speediness and accuracy that can eliminate the fussy operation process in routine tests. The main conclusions summarized from the study are as follows. First, the...     

脱硝效率与催化剂层数

目前,燃煤电厂新、扩建工程同步脱硝已进入设计日程。其中脱硝效率应如何确定已成为首要课题,在脱硝效率确定以后,如何在采用SCR工艺时合理确定其安装和预留层数,尚存在争论,由于脱硝装置造价及运行成本中,催化剂均占主要部分,更成为重要课题之一。     

基于空间状态向量的定子绕组短路辨识

定子绝缘层的瑕疵是电机故障的主要因素.异步电机的检测模型能够检测出少量绕组线圈的短路故障.借助卡尔曼滤波器模型对相电流进行分析,能够准确辨识出微小的短路电流,进而采取有效措施检测故障,防止事故的发生.     

某变电站设备支架倾斜事故分析

某变电站地基条件相对较差,且存在膨胀土.设备支架地基原本采用CFG桩复合地基处理,但施工单位将CFG桩改为大直径桩,且人工成孔,设备基础施工完成后约半年,当设备安装完毕试送电时发现,设备基础周边地面有裂隙,支架倾斜,文中通过分析事故原因,进而讨论CFG复合地基处理的机理,并提出相应解决方案.     

Structure and ferroelectric property of Nb-doped SrBi4Ti4O15 ceramics

Nb-doped SrBi₄Ti₄O₁₅ (SBT) was produced by conventional method. Structural and ferroelectric properties of SBT were examined as a function of niobium composition. Analyzing the structure futures of SBT by XRD, XPS and Raman spectrum, Nb⁵⁺ substituted Ti⁴⁺ to form NbO₆ octahedron and did not change the structure of SBT. The XRD patterns indicated the formation of the single phase of SBT for x = 0.01and 0.03 and secondary phase of Sr₃Ti₂O₇ appeared when x > 0.1. To compare the effect of Nb doping, the ferroelectric properties (hysteresis loop, piezoelectric coefficient) of Nb-doped SBT were measured. The SBT doped with x = 0.15 was found to exhibit higher remanent polarization with d ₃₃ = 17 pC/N.     

Deposition thickness based high-throughput nano-imprint template

International Technology Roadmap for Semiconductors 2003 projected nano-imprint lithography has the potential of high throughput, sub-20 nm resolution, and low cost [S.Y. Chou, P.R. Krauss, P.J. Renstrom, Appl. Phys. Lett. 67 (1995) 3144; Science 272 (1996) 85, J.A. Rogers, C. Mirkin, Mater. Res. Bull. 26 (2001)]. For nano-imprint lithography, a template with 1X resolution is required. The existing industrial infrastructure for supporting deep ultra violet 4X photo masks by e-beam and/or a laser beam scanning writer does not offer pitch (center-to-center distance of an array of patterned lines) less than ∼60 nm [<http://public.itrs.net/2003ITRS>]. For nano-imprint lithography to be accepted across the industry, a reproducible simple fabrication process to make a high resolution, single emboss template is essential [L. Jay Guo, J. Phys. D: Appl. Phys. 37 (2004) R123-R141]. Here we show, a general fabrication method and fabricated nano-imprint templates with sub-15 nm template line width and 10 nm pitch length through out the entire 200 mm wafer, varying the deposition thickness of multiple alternate films, using atomic layer deposition. Although multilayer nano-imprint templates and their exciting use have been demonstrated, [W.J. Dauksher et al., J. Vac. Sci. Technol. B 22 (2004) 3306, B. Heidari, et al., The 49th international conference on electron, ion and photon beam technology and nanofabrication, Orlando, Florida, 2005, William M. Tong, et al., Proc. SPIE 5751 (2005) 46-55, N.A. Melosh, A. Boukai, F. Diana, B. Gerardot, A. Badolato, P.M. Petroff, J.R. Heath, Science 300 (2003) 112] such a small pitch was not shown and either complex lattice mismatch-based epitaxially grown films or unconventional etch chemistry was used. The bare necessity was a simple and economical fabrication process for a high throughput nano-imprint template. In that context, we have developed a template fabrication process using classical micro-fabrication techniques. Successful use of these techniques made the template fabrication process simple, economical, and expedient. Also a novel technique to provide flexible and accurate alignment for nanowire patterning has been described. In this technique, nanowire patterning is accomplished on the entire wafer with a single impression. Industry level batch-fabrication of our scheme illustrates its reproducibility and manufacturability. We anticipate, this simple, economical and time saving technique will help researchers and developers to perform their experiment on nano-scale feature patterned substrates easily and conveniently.     

带p埋层表面注入硅基LDMOS模型与优化

提出一种带p埋层的表面注入硅基LDMOS高压器件新结构,称为BSI LDMOS(surface implanted LDMOS with p buried layer).通过表面注入n+薄层降低导通电阻,p埋层不但改善横向表面电场分布,提高击穿电压,而且增大漂移区优化浓度.求解电势的二维Poisson方程,获得表面电场和击穿电压的解析式,研究结构参数对表面电场和击穿电压的影响,数值与解析结果吻合较好.结果表明:与常规结构相比较,BSI LDMOS大大改善了击穿电压和导通电阻的折衷关系.