Performances of carbon nanotube field effect transistors with altered channel length

The influence of channel length on the performances of carbon nanotube field effect transistors(CNT-FETs) has been studied.Buffered oxide etching was used to remove approximately a 60 nm layer from the original 100 nm silicon dioxide layer,to thin the dielectric layer of the back gate.Channel length of the CNT-FETs was changed along with the etching process.The dependence of drain-source current on gate voltage was measured to analyze the performance of the CNT-FETs,including the transconductance,carrier mo...     

Microfabrication of polytetrafluoroethylene using SR direct etching

Polytetrafluoroethylene (PTFE) is a very attractive material for various fields because of its chemical resistance, insulation properties, and hydrophobic properties. However, it is difficult to fabricate PTFE microstructures with conventional techniques such as semiconductor processes or micromachining. We have succeeded in the fabrication of high‐aspect‐ratio microfluidics parts from PTFE by direct in‐vacuum photo‐etching utilizing synchrotron radiation (SR) at energy levels from 2 to 12 keV. This paper presents an analysis of the mechanisms of the PTFE microfabrication process and describes newly discovered processing characteristics of PTFE. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 178(4): 49–54, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21152     

Wet-chemical etching of (11 $$\bar 2$$ 0) ZnO films0) ZnO films

This paper describes the optimized process of wet-chemical etching of a ZnO film grown on an r-plane sapphire. Different etchants and solution ratios have been used to achieve controllable etching rate and steep etching profile. With selected etching solutions, the etching profiles of epitaxially grown ZnO films (>1.3 μm) are improved. Using Al instead of photoresist as the mask generates a steeper etching slope. Maximal 1:1 vertical/horizontal ratio (45°) has been achieved. X-ray photoelectron spectroscopy (XPS) and sheet resistance measurements show that this wet-chemical etching process has negligible influence on the modification of the physical and chemical properties of the etched surface.     

A Plasma‐Etching Process Modeling Via a Polynomial Neural Network

A plasma is a collection of charged particles and on average is electrically neutral. In fabricating integrated circuits, plasma etching is a key means to transfer a photoresist pattern into an underlayer material. To construct a predictive model of plasma‐etching processes, a polynomial neural network (PNN) is applied. This process was characterized by a full factorial experiment, and two attributes modeled are its etch rate and DC bias. According to the number of input variables and type of polynomials to each node, the prediction performance of the PNN was optimized. The various performances of the PNN in diverse environments were compared to three types of statistical regression models and the adaptive network fuzzy inference system (ANFIS). As the demonstrated high‐prediction ability in the simulation results shows, the PNN is efficient and much more accurate from the point of view of approximation and prediction abilities.     

电子显微镜技术表征树脂中橡胶相的显微结构形态

本文采用染色和化学刻蚀技术,通过透射电子显微镜(TEM)和扫描电子显微镜(SEM)对ABS树脂、高抗冲聚苯乙烯(HIPS)树脂、乙丙共聚聚丙烯SPl79、AWl91树脂中橡胶相的显微结构形态进行表征.结果表明,当树脂中橡胶相含双键时,采用硫化染色和四氧化锇(OsO4)染色技术,均能观察到树脂中橡胶相的显微结构形态,且采...     

Effect of High-Density Plasma Process Parameters on Carrier Transport Properties in <Emphasis Type="Italic">p</Emphasis>-to-<Emphasis Type="Italic">n</Emphasis> Type Converted Hg<Subscript>0.7</Subscript>Cd<Subscript>0.3</Subscript>Te Layer

Exposure of p-type HgCdTe material to Ar/H₂-based plasma is known to result in p-to-n conductivity-type conversion. While this phenomenon is generally undesirable when aiming to perform physical etching for device delineation and electrical isolation, it can be used in a novel process for formation of n-on-p junctions. The properties of this n-type converted material are dependent on the condition of the plasma to which it is exposed. This paper investigates the effect of varying the plasma process parameters in an inductively coupled plasma reactive ion etching (ICPRIE) tool on the carrier transport properties of the p-to-n type converted material. Quantitative mobility spectrum analysis of variable-field Hall and resistivity data has been used to extract the carrier transport properties. In the parameter space investigated, the n-type converted layer carrier transport properties and depth have been found to be most sensitive to the plasma process pressure and temperature. The levels of both RIE and ICP power have also been found to have a significant influence.     

非制冷红外焦平面阵列读出电路的BCB牺牲层接触平坦化(英文)

研究了一种基于BCB材料的牺牲层接触平坦化技术,用于红外焦平面阵列Post CMOS工艺之前对读出电路表面的平坦化,以利于微测辐射热计微桥阵列与读出电路的集成。利用该方法成功将2μm的电路表面突起,平坦化为表面起伏56 nm的平面,可替代会给器件带来颗粒和损伤的化学机械抛光(CMP)技术。并在该平坦层上方成功进行了非晶硅敏感薄膜的沉积、微桥结构的图形化以及同时作为牺牲层的BCB的释放。通过实验研究了BCB膜层的厚度与转速、固化温度的关系,实验发现BCB的收缩率随温度小范围变化,约为30%。研究了BCB的等离子刻蚀特性,表明该材料适合用等离子刻蚀的方法进行接触孔的刻蚀和牺牲层释放。最后,利用BCB牺牲层接触平坦化技术成功地在读出电路(ROIC)芯片上制作了160×120面阵的非制冷红外焦平面阵列。     

Plasma etching of copper films at low temperature

Experimental verification of a low temperature (<20 °C), reactive plasma etch process for copper films is presented. The plasma etch process, proposed previously from a thermochemical analysis of the Cu-Cl-H system, is executed in two steps. In the first step, copper films are exposed to a Cl₂ plasma to preferentially form CuCl₂, which is volatilized as Cu₃Cl₃ by exposure to a H₂ plasma in the second step. Plasma etching of thin films (9 nm) and thicker films (400 nm) of copper has been performed; chemical composition of sample surfaces before and after etching has been determined by X-ray photoelectron and flame atomic absorption spectroscopies.     

用于ICF驱动器的色分离光栅的制作

介绍了色分离光栅的设计原理,并对其制作工艺进行了研究.用套刻法以能量为450 eV、束流密度为80 mA/cm2、30°入射角的离子束对100 mm×100 mm石英基片进行刻蚀,制作出了周期为300 μm色分离光栅.实验测得零级次上3ω(351 nm)光的归一化衍射效率达到了91.9%.结果表明,这套工艺方法在制作高衍射效率的CSG是可行的,并且具有刻蚀图形分辨率高、侧壁较陡等优点,为进一步制作高衍射效率的色分离光栅提供了参考.     

Detailed structural analysis of GaAs grown on patterned Si

The growth of GaAs on patterned Si substrates is essential for the integration of GaAs and Si devices. Moreover this growth may have to be done in wells to planarize the surfaces of the Si and GaAs devices for their interconnection. In this study, GaAs is grown by MBE on such patterned Si substrates, with window width down to 3 μm, and a complete structural characterization of the material is made by electron microscopy. In every case, SEM observations show a very good definition of the pattern by the contrast of the flat surface of the monocrystalline GaAs compared to the very rough surface of the polycrystalline GaAs. Cross-sectional observations by STEM or TEM on non-etched samples reveal that the quality of the monocrystalline GaAs is at least as good in terms of defect density as that of the standard GaAs on Si. On samples etched with a plasma to produce wells, grains often form against the Si sidewall. Chemical etching with lateral etching avoids contact of the growing GaAs with the Si sidewall and subsequent grain formation. The crystalline quality obtained on etched samples is not as good as on non etched samples. A way of preparing the wells to improve this crystalline quality is proposed.