点阴极电场辅助阳极连接中的紧密接触面积和电流

用等效电路的方法研究了点阴极情况下的电场辅助阳极连接效应，计算了连接电流，连接孕育期和紧密接触面积，本文结果表明，连接初期电流迅速衰减，随后缓慢变小，直至某一稳定值，孕育期随温度上升指数下降，连接温度高时，孕育期将难以观察到；待连接表面之间紧密接触面积随时间延长而非线性扩展，紧密接触区域增大时，其边界向外推进速度渐小，而接触面积增加渐快。     

浅谈酶在非接触印刷废纸脱墨中的应用

简要地介绍了纤维素酶、半纤维素酶和淀粉酶在非接触印刷废纸脱墨中的研究及其应用     

液晶显示驱动电路中Fibonacci型电荷泵单元

本文中所设计的电荷泵将用于手机液晶显示驱动模块中.通过对Fibonacci型电荷泵上升时间的估算,对减小上升时间和动态功耗进行折中考虑,本文提出优化开关频率的方法.用1.2μm CMOS双阱工艺参数对所设计的电荷泵进行模拟,结果表明这个电荷泵具有较快的上升速度和较高的效率.通过提高V_GS电平和保证开关管的衬底始终接在最高电位上,文中提出了一种新型Fibonacci电荷泵,它可以正常工作在从1.2V到5V变化的多种电源电压下.     

Generation of Technology-Independent Retargetable Analog Blocks

This paper introduces a complete methodology for retargeting of analog cells to different sets of specifications. This methodology is technology-independent, thus allowing the migration, from one technology to another, of the circuit under retargeting. Careful integration of the device sizing and layout generation tasks via the incorporation of layout constraints during the sizing process allows to generate fully functional designs in a few minutes. The methodology is illustrated via the retargeting of a fully-differential Miller-compensated two-stage operational amplifier for a new set of specifications and two different technological processes.An erratum to this article can be found at     

基于IP核复用技术的SoC设计

概述了国内外IP产业的发展情况,论述了我国发展IP核复用技术SoC设计的可能性和必要性,指出我国急需发展的关键芯片及IP核种类.     

基于充放电原理实现的微电容测量电路

具有抗分布电容以及简单实用等特性的充放电电路是目前微电容测量中广泛采用的一种测量电路。本文对基于充放电原理的微电容测量电路进行了深入研究，并介绍一种基于充放电原理的实用电路。     

长距离管线监测系统的一种智能化过流防护方法

介绍了长距离管线监测系统的一种智能化过流防护方法，详细说明其电路设计原理及相关元件的选择，并与串联自复过流保护元件方式相比较，分析其整体性能，说明其具有响应速度快，安全可靠等特点。     

界面流法计算反应堆六角形燃料组件中子通量密度分布

利用界面流法计算两维六角形轻水堆燃料组件中子通量密度分布。子区内中子源在空间上采用二次分布近似，还考虑了六角形组件周边水隙对组件内中子通量密度的影响。根据提出的模型，编制了TPHEX－E程序，并对一些轻水堆六角形组件问题作了计算，计算结果与蒙特卡罗方法计算结果进行了比较，符合良好。本程序可用于六角形轻水堆燃料组件计算。     

大功率晶体管的保护电路

大功率晶体管调速系统中作为开关元件使用时，共优点是开关频率比可控硅的高，但是不注意保护就容易损坏。着重研究过电流故障，并对保护作用的影响进行了分析，进而提出了防止过电流的方法和工作原理。     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.