不同硅/铝比ZSM-5分子筛对烷烃和环烷烃催化裂解性能的影响

以硅/铝摩尔比（n(SiO2)/n(Al2O3)=24的ZSM 5分子筛为母体,通过酸处理脱铝制备了具有不同硅/铝摩尔比(50、85、110、140)的ZSM-5分子筛,通过X射线衍射(XRD)、扫描电镜(SEM)、氨气程序升温脱附(NH3-TPD)、吡啶红外吸附(Py-FTIR)、N₂吸附-脱附等手段对其进行表征,考察其应用于正辛烷和乙基环己烷催化裂解反应的性能差异。结果表明,正辛烷和乙基环己烷的转化率与ZSM-5分子筛硅/铝比存在较好的对应关系,即硅/铝比越低、酸量越高,转化率越高;但ZSM-5分子筛硅/铝比低、酸量过多会导致非选择性副反应发生,降低目的产物低碳烯烃收率和选择性。不同硅/铝比ZSM-5分子筛在正辛烷和乙基环己烷催化裂解反应中显示出不同的催化性能,对于相同碳数的烷烃正辛烷和乙基环己烷,由于其分子结构不同,所适宜的硅/铝比不同;在相同硅/铝比分子筛条件下,环烷烃乙基环己烷的总体反应活性低于相对应的直链烷烃正辛烷;正辛烷在ZSM-5-85分子筛上具有更优异的催化裂解反应性能,乙基环己烷在ZSM-5-50分子筛上具有更优异的催化裂解反应性能。     

Surface activation using oxygen and nitrogen radical for Ge-Si Avalanche photodiode integration

In this work, an alternative method for producing the single crystalline Ge-Si Avalanche photodiodes (APD) with low thermal budget was investigated. Structural and electrical investigations show that low temperature Ge to Si wafer bonding can be used to achieve successful APD integration. Based on the surface chemistry of the Ge layer, the buried interfaces were investigated using high resolution transmission electron microscopy as a function of surface activation after low temperature annealing at 200 and 300 °C. The hetero-interface was characterized by measuring forward and reverse currents.     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

面向三维集成电路版图设计的EDA插件研究

三维集成是未来微电子系统的发展方向。但是,现阶段的EDA软件如Cadence等却没有覆盖整个三维集成电路版图设计流程。为了更好的满足工程师在三维集成电路设计中的需要,本文基于SKILL语言,对业界主流版图设计工具Cadence Virtuoso进行二次开发,开发出能辅助三维集成电路设计的EDA插件。该EDA插件主要包括三种功能：自动对齐,自动打孔和三维可视化技术。最终,本文在三维集成电路的背景下设计两个并联的反相器。实验表明,该EDA插件能够满足三维集成电路设计的需求,简化了三维集成电路版图设计的过程,具有很好的易用性。     

利用固相反应法在硅片上制备硅酸锌发光薄膜及表征

采用与硅集成工艺相兼容的固相反应方法在硅衬底上制备了未经掺杂及掺锰的硅酸锌薄膜 .XRD测试和UV - Vis吸收谱测试证明在高于 880℃的温度下热处理 ,可以获得结晶状态很好的硅酸锌薄膜 .光致发光光谱分析表明 ,未掺杂的薄膜在紫外波段有较弱的发射 ,而掺锰的硅酸锌薄膜在可见光波段有很强的光致发射 .由于硅酸锌薄膜在高温下非常稳定 ,可以与硅集成电路工艺兼容 ,而且发光强度高 ,因此在制作硅基光电集成器件方面有非常大的应用前景     

Si基MOCVD生长AlN深陷阱中心研究

通过PL 谱和Raman谱对MOCVD生长Si基Al N的深陷阱中心进行了研究,发现三个深能级Et1 ,Et2 ,Et3,分别在Ev 上2 .6 1,3.10 ,2 .11e V.Et1 是由氧杂质和氮空位(或Al间隙原子)能级峰位靠近重合共同引起的,Et2 、Et3都是由于衬底Si原子扩散到Al N引起的.在Si浓度较低时,Si主要以取代Al原子的方式存在,产生深陷阱中心Et2 .Si浓度高于某个临界浓度时,部分Si原子以取代N原子位置的方式存在,形成深陷阱中心Et3.实验还表明,即使经高温长时间退火,Al N中Et1 和Et2 两个深陷阱中心也是稳定的     

氮化硅基陶瓷材料抗穿甲破坏实验研究

陶瓷复合材料是轻型装甲战斗车辆的装甲材料之一 ,介绍了氮化硅陶瓷材料靶板的制备工艺和方法 ,以及使用其进行穿甲试验的全过程 ,试验和计算结果表明 ,氮化硅陶瓷靶以其良好的抗穿甲破坏能力成为了一种很有发展前途的装甲防护材料     

铒,氧共注a—Si：H和a—SiCx：H的1.54μm光致发光

在ａ－Ｓｉ：Ｈ和ａ－ＳｉＣｘ：Ｈ中共注稀土铒和氧。３００℃和４００℃热退火后，测得了来自发光中心Ｅｒ３＋内层４ｆ电子跃迁的１．５４μｍ光致发光。４００℃是较好的退火温度。随着碳含量的增加，发光强度逐渐减弱，这可能是由于碳的引入减弱了间隙氧退火时的迁移能力所致。     

激光合成Al_2O_3-WO_3陶瓷材料的显微分析

用Ｘ射线衍射等技术分析了激光合成Ａｌ２Ｏ３－ＷＯ３陶瓷材料，结果表明在激光合成样品中形成柱状晶，而常规工艺和Ｎ２气氛中烧结样品不含有柱状晶，柱状晶的成分主要是Ａｌ２Ｏ３。进一步的分析表明Ａｌ２Ｏ３－ＷＯ３陶瓷合成样品的导电相是ＡｌｘＷＯ３。     

Molecular-beam epitaxial growth of HgCdTe infrared focal-plane arrays on silicon substrates for midwave infrared applications

Molecular beam epitaxy has been employed to deposit HgCdTe infrared detector structures on Si(112) substrates with performance at 125K that is equivalent to detectors grown on conventional CdZnTe substrates. The detector structures are grown on Si via CdTe(112)B buffer layers, whose structural properties include x-ray rocking curve full width at half maximum of 63 arc-sec and near-surface etch pit density of 3–5 × 10⁵ cm⁻² for 9 μm thick CdTe films. HgCdTe p⁺-on-n device structures were grown by molecular beam epitaxy (MBE) on both bulk CdZnTe and Si with 125K cutoff wavelengths ranging from 3.5 to 5 μm. External quantum efficiencies of 70%, limited only by reflection loss at the uncoated Si-vacuum interface, were achieved for detectors on Si. The current-voltage (I-V) characteristics of MBE-grown detectors on CdZnTe and Si were found to be equivalent, with reverse breakdown voltages well in excess of 700 mV. The temperature dependences of the I-V characteristics of MBE-grown diodes on CdZnTe and Si were found to be essentially identical and in agreement with a diffusion-limited current model for temperatures down to 110K. The performance of MBE-grown diodes on Si is also equivalent to that of typical liquid phase epitaxy-grown devices on CdZnTe with R₀A products in the 10⁶–10⁷ Θ-cm² range for 3.6 μm cutoff at 125K and R₀A products in the 10⁴–10⁵ Θ-cm² range for 4.7 μm cutoff at 125K.