用于快速门控制电荷积分型ADC的电荷-电压变换器——QVC

本文描述了通过模数转换器(ADC)与电荷电压变换器(QVC)组合来进行脉冲形状甄别的一种方法,并较为详细地介绍了电路的工作原理。     

Characterization of high-quality polycrystalline diamond and its high FET performance

We characterized high-quality polycrystalline diamond with large grains and fabricated polycrystalline diamond field effect transistors (FETs). The polycrystalline diamond had (110) preferred orientation, and its typical grain size was  100 μm. Well-resolved free exciton related emissions were observed at room temperature in cathodoluminescence. The FETs showed extremely high DC and RF performance. The cut-off frequency for current gain (f_T) and power gain (f_max) were 45 and 120 GHz, respectively. The maximum drain current (I_DS) was 550 mA/mm. These values are the highest among diamond FETs, including those fabricated from single-crystal diamond. These results suggest that high-quality polycrystalline diamond, whose maximum size is 4 in., is very promising for diamond electronic devices.     

Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators

This paper presents the successful use of ZnS/ZnMgS and other II–VI layers (lattice-matched or pseudomorphic) as high-k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO _x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO _x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.     

锗纳米线的性能与应用

重点分析讨论了锗纳米线在电学、光学、光电导等特性及其在场效应晶体管制造方面的研究应用现状与最新进展。综合分析表明,未经处理的锗纳米线表面存在一层氧化物及缺陷,与电极连接时欧姆接触性能较差,在制备锗纳米线器件以前必须对锗纳米线表面进行钝化以便沉积电极;对锗纳米线进行掺杂可以改善Ge纳米线的性能,制造出实用Ge纳米线器件。指出在一根纳米线上生长硅/锗半导体纳米线形成硅/锗半导体界面,直接用单根纳米线制造具有完整功能的电子器件是将来重要的研究方向。     

基于FLM3135-18F的S波段微波功率放大器设计

介绍了基于阻抗内匹配GaAs FET微波场效应管FLM3135-18F全固态线性高功率放大器的设计,介绍了功率放大器系统原理以及FLM3135-18F.     

Micro FET pressure sensor manufactured using CMOS-MEMS technique

The fabrication of a micro field effect transistor (FET) pressure sensor using the commercial 0.35 μm complementary metal oxide semiconductor (CMOS) process and a post-process has been investigated. The pressure sensor is composed of 16 sensing cells in parallel, and each sensing cell includes a suspended membrane and an NMOS. The suspended membrane is the movable gate of the NMOS. The pressure sensor needs a post-process to obtain the suspended membrane after the CMOS process. The post-process employs etchants to etch the sacrificial layers to release the suspended membrane, and then a low-pressure chemical vapor deposition (LPCVD) parylene is used to seal the etching holes in the pressure sensor. The pressure sensor produces a change in current when applying a pressure to the sensing cells. Experimental results show that the pressure sensor has a sensitivity of 0.022 μA/kPa in the pressure range of 0–500 kPa.     

检测仪器中接收机低噪声放大器的发展

由于低噪声放大器（LNA）在各类仪器接收机中起着重要的作用,近几十年来人们在低噪声放大器的研究方面不断取得进步,尤其是在低噪声性能方面,从早期复杂、笨重的低噪声放大器发展到现在的高电子迁移率晶体管放大器,其频带和噪声性能方面都有了明显的提高.本文主要回顾低噪声放大器研究的进展,并对未来的发展方向和前景做了展望.     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

超宽禁带半导体金刚石功率电子学研究的新进展

以SiC/GaN为代表的第三代半导体功率电子学已成为当今功率电子学创新发展的主流,超宽禁带半导体金刚石功率电子学将有可能成为下一代固态功率电子学的代表,受到研究人员的广泛关注。介绍了金刚石功率电子学的最新进展,如金刚石单晶、金刚石化学气相沉积同质和异质单晶外延、金刚石多晶外延、金刚石二极管、金刚石MOSFET、金刚石结型场效应晶体管、金刚石双极结型晶体管、金刚石逻辑电路、金刚石射频场效应晶体管和金刚石上GaN HEMT等。还介绍了金刚石材料的大尺寸、低缺陷和p型及n型掺杂等制备技术,金刚石新器件结构设计,金刚石新器件工艺,转移掺杂H端-金刚石沟道和金刚石/GaN界面热阻等研究成果。分析了金刚石功率电子学的发展由来、关键技术突破和发展态势。     

Design of Parasitic Inductance Reduction in GaN Cascode FET for High‐Efficiency Operation

This paper presents a method of parasitic inductance reduction for high‐speed switching and high‐efficiency operation of a cascode structure with a low‐voltage enhancement‐mode silicon (Si) metal–oxide–semiconductor field‐effect transistor (MOSFET) and a high‐voltage depletion‐mode gallium nitride (GaN) field‐effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.