纳米级CMOS电路的漏电流及其降低技术

随着CMOS工艺的进一步发展,漏电流在深亚微米CMOS电路的功耗中变得越来越重要.因此,分析和建模漏电流的各种不同组成部分对降低漏电流功耗非常重要,特别是在低功耗应用中.本文分析了纳米级CMOS电路的各种漏电流组成机制并提出了相应的降低技术.     

Reducing leakage power with BTB access prediction

This paper investigates three architectural methods to reduce the leakage power dissipated by the BTB data array. The first method (called here window) periodically places the entire BTB data array into drowsy mode. A drowsy entry is woken up by the first access in the time interval and remains active for the remainder of the interval (window). There is an associated performance loss which is related to the size of the window, since there is a delay when a specific line must be woken up. The second method, awake line buffer (ALB), limits the number of active BTB entries to a predetermined maximum. While this reduces power dissipation it comes with a performance penalty that is relative to the size of the buffer. ALB, however, reduces the power dissipation of the data array more than the window method. The third method, 2-level ALB (2L-ALB), uses a two level buffer with the identical number of combined entries as the previous method. This method exploits the fact that many branches operate numerous times in a fixed sequence. By predicting the next BTB access, 2L-ALB achieves further reduction in leakage power without incurring any further performance loss, compared to the ALB method.     

Scaling of analog LDPC decoders in sub-100 nm CMOS processes

Analog implementations of digital error control decoders, generally referred to as analog decoding, have recently been proposed as an energy and area competitive methodology. Despite several successful implementations of small analog error control decoders, little is currently known about how this methodology scales to smaller process technologies and copes with the non-idealities of nano-scale transistor sizing. A comprehensive analysis of the potential of sub-threshold analog decoding is examined in this paper. It is shown that mismatch effects dominated by threshold mismatch impose firm lower limits on the sizes of transistors. The effect of various forms of leakage currents is also investigated and minimal leakage current to normalizing currents are found using density evolution and control simulations. Finally, the convergence speed of analog decoders is examined via a density evolution approach. The results are compiled and predictions are given which show that process scaling below 90 nm processes brings no advantages, and, in some cases, may even degrade performance or increase required resources.     

Syntheses,Properties, and Potential Applications of Multicomponent Magnetic Nanoparticles

Multicomponent hybrid nanostructures that contain two or more nanometer‐scale components have attracted much attention recently owing to the synergistic properties induced by interactions between these different nanometer‐scale objects. Herein, we give an overview of the efforts to synthesize multicomponent nanoparticles with at least one component being magnetic, and focus on our recent developments. The syntheses are based on heterogeneous nucleation and growth of a second and third component onto seed nanoparticles. These multicomponent nanoparticles show interesting magnetic, magneto‐optical, plasmonic, and semiconducting properties that can be modulated by interfacial interactions between different nanocomponents. This opens up a new avenue to advanced multifunctional nanomaterials for device concepts and applications.     

Parameter variation aware hybrid TFET-CMOS based power gating technique with a temperature variation tolerant sleep mode

In this work, we discuss the origin and temperature dependence of various mechanisms behind the flow of leakage current in two topologies of TFET – basic TFET and pocket doped TFET. It is shown that the leakage current of pocket doped TFET shows relatively less variations with change in temperature when compared with MOSFET and basic TFET, and hence they can be deployed in low voltage temperature variation prone applications. But, this advantage of pocket-doped TFET is overshadowed by the huge sensitivity of its ON-state current towards variations in doping concentration at the tunnel junction. Hence, the fabrication of the TFET based circuits requires a negotiation with the yield and cost of the fabrication process. In order to mitigate this issue, we propose a hybrid TFET-CMOS based power gating technique. The hybrid technique utilizes a minimum number of TFETs to reduce the sleep mode leakage current, while enabling a temperature variation tolerant sleep mode at a supply voltage of 0.6 V.     

Magnetic levitation with unlimited omnidirectional rotation range

We have realized a magnetic levitation device in which the motion of a levitated body can be stably controlled in any orientation, with no limits on its spatial rotation range. The system consists of a planar array of cylindrical coils on a fixed base, a levitated frame containing disc magnets and LED position markers, and an optical motion tracking sensor for feedback control of levitation. This system combines the capabilities of fine positioning, vibration isolation, and a spherical motor, with potential applications in omnidirectional antenna and camera pointing, user interaction, manipulation, and simulated spaceflight dynamics and control. The device design is presented including the magnet and coil configuration, analysis and control methods, and position and rotation trajectory control results.The system development process consisted of numerical analysis of electromagnetic forces and torques between coils and magnets, to find the maximum required coil currents for levitation and the condition numbers of the transformation matrices between coil currents and forces and torques generated on the levitated body, for various configurations of coils and magnets, over their full 3D translation and rotation ranges. As a result, a magnetic levitation setup consisting of an array of 27 coils and a levitated object with six disk-shaped permanent magnets was selected. The setup achieved levitation in six degrees of freedom and unlimited rotation about any axis at a fixed height of 40 mm (a 4 mm minimum height above the coil array). The performance was verified with levitated trajectory following rotation command experiments in roll, pitch, yaw, and including 360° rotations about non-principal axes.     

Introduction of a new technique for simultaneous reduction of the delay and leakage current in digital circuits

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology.We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.     

真空灭弧室横向磁场触头间磁吹力的计算分析

对螺旋槽型和杯状型两种横磁触头进行了研究,仿真分析了不同电弧位置和触头结构参数下触头间磁场的分布,同时计算分析了触头间电弧所受的磁吹力,可为横向磁场触头的研究与应用提供参考。     

Electromodulation and magnetomodulation of exciton dissociation in electron donor (starburst amine) : electron acceptor (bathocuproine) system

Electric field dependencies of electromodulated photoluminescence and photocurrents as well as the magnetic field effects on photocurrents, photovoltaic characteristics, electromodulated photoluminescence and photoluminescence have been investigated in vacuum evaporated films of m-MTDATA:BCP (4,4′,4″-tris(N-(3-methylphenyl)-N-phenylamino)triphenylamine and bathocuproine) system. The electromodulation processes do remain in accordance with Onsager as well as with the Sano–Tachiya–Noolandi–Hong formalisms of electron–hole pair separation. While the electromodulated photocurrents are due to operation of both long-radius and short-radius e–h pairs, the electromodulated photoluminescence quenching is related to merely short-radius fraction of the e–h pairs involved in the exciplex creation process. The photocurrents, photovoltaic characteristics, photoluminescence and electromodulated photoluminescence are influenced by external magnetic field of the hyperfine coupling (HFC) scale which modulates the singlet–triplet intersystem crossing of long-radius e–h pairs.     

Formation of n-channel polycrystalline-Si thin-film transistors by using retrograde channel scheme with double implantation

Excellent n-channel poly-Si thin-film transistors (poly-Si TFTs) have been formed by using retrograde channel scheme with channel doping implantation and extra counter-doping implantation. As compared to the conventional sample with undoped channel layer, a much smaller leakage current can be achieved by boron-doping the poly-Si channel layer, due to a significantly reduced depletion region. However, the on-state characteristics are degraded. A retrograde channel scheme, implemented by further phosphorus counter-doping the surface of the boron-doped channel layer, is proposed for lowering the channel surface doping concentration without changing the bulk channel doping concentration. By using the retrograde channel scheme, an off-state leakage current as low as that for the normal channel-doping scheme may be achieved, while yielding excellent on-state I-V transfer characteristics.