Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.     

CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing

As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture.     

气体加速泵排水采气工艺技术应用与展望

介绍气体加速泵的结构、工艺原理及现场试验情况.通过室内实验和研究,并在蜀南气矿S1、S2井进行了先导性试验,对其在有水气田的应用作出了适应性评价.     

Juvenile competence to stand trial evaluations: A survey of current practices and test usage among psychologists.

What is the current standard of practice for evaluations of juvenile competence to stand trial (JCST)? The present study surveyed psychologists regarding the practices used when conducting JCST evaluations. Respondents rated the importance of 17 elements that might be included in a JCST evaluation report. Of these elements, 7 were considered essential by 70% or more of respondents, with 9 additional elements rated as either essential or recommended. A majority of respondents felt that the use of psychological and forensic instruments was important. A list of tests used is provided, and the implications for the development of standards and policy are discussed to provide practitioners with additional knowledge that will help to further the state of the discipline. (PsycINFO Database Record (c) 2010 APA, all rights reserved)     

VLSI Implementation of Forward Error Control Technique for ATM Networks

In asynchronous transfer mode (ATM) networks, fixed length cells of 53 bytes are transmitted. A cell may be discarded during transmission due to buffer overflow or a detection of errors. Cell discarding seriously degrades transmission quality. The quality degradation can be reduced by employing efficient forward error control (FEC) to recover discarded cells. In this paper, we present the design and implementation of decoding equipment for FEC in ATM networks based on a single parity check (SPC) product code using very‐large‐scale integration (VLSI) technology. FEC allows the destination to reconstruct missing data cells by using redundant parity cells that the source adds to each block of data cells. The functionality of the design has been tested using the Model Sim 5.7cXE Simulation Package. The design has been implemented for a 5 ° 5 matrix of data cells in a Virtex‐E XCV 3200E FG1156 device. The simulation and synthesis results show that the decoding function can be completed in 81 clock cycles with an optimum clock of 56.8 MHz. A test bench was written to study the performance of the decoder, and the results are presented.     

一个用户接口管理系统

本文介绍了一个用户接口管理系统NUUIMS的设计和实现.重点叙述了该系统基于规范化目标用户接口模型的设计思想,系统组成及描述方法.文章也讨论了使用NUUIMS设计而成的用户接口的特点.     

土壤源热泵取热的实验研究

通过广泛分析国内外对土壤源热泵实验研究的现状,建立了可以模拟多个地区、多种运行工况的土壤源热泵沙箱实验台,并进行了绝热边界工况短期内取热的实验研究。     

The Effect of the Estimation on Goodness‐of‐Fit Tests in Time Series Models

Abstract. We analyze, by simulation, the finite‐sample properties of goodness‐of‐fit tests based on residual autocorrelation coefficients (simple and partial) obtained using different estimators frequently used in the analysis of autoregressive moving‐average time‐series models. The estimators considered are unconditional least squares, maximum likelihood and conditional least squares. The results suggest that although the tests based on these estimators are asymptotically equivalent for particular models and parameter values, their sampling properties for samples of the size commonly found in economic applications can differ substantially, because of differences in both finite‐sample estimation efficiencies and residual regeneration methods.     

浅议铵梯炸药质量检验中的三个问题

文章探讨了GB 12437-2000标准规定的产品检验项目中,中包浸水试验的科学性问题和对批产品进行抽样时的样本代表性问题以及使用多段爆速仪测试爆速时应注意的样本量问题.     

提高小样试织质量的措施

介绍了纺织品小样试织时，为了提高试织质量在经纬纱准备及织造工序时所采取的一些措施。