避免发生芯片裂纹的倒装片BGA技术概述

介绍了把断裂力学法应用于倒装片BGA的设计方法。概述了一些关键的材料特性和封装尺寸对倒装片BGA芯片裂纹的影响作用，从而断定基板厚度和芯片厚度是倒装片BGA芯片发生裂纹的两个最重要的因素。     

基于微控制器的塑料光子晶体光纤拉丝塔加热炉的新型设计

塑料光子晶体光纤(Plastic Photonic Crystal Fibers,PPCF)是一种新型的塑料光纤,其主要特征是在包层中有形状、大小、排列不同的微结构孔。拉丝塔是制作塑料光子晶体光纤的重要装置,而加热系统则是拉丝塔的关键组成部分。制作塑料微结构光纤要求加热系统的温度场呈特殊分布,这样能避免孔塌陷。本文中我们设计了一种基于微控制器(Micro Controller Unite,MCU)的加热系统。该系统采用分区加热,其温度曲线比较理想,满足了制作不同结构MPOF时的需要。     

基于Ce∶YAG晶体的掺Ce光纤拉制技术

基于管棒法(Rod-in-Tube)技术,以Ce∶YAG晶体作为芯棒,纯石英玻璃管作为套管,利用石墨炉、拉丝塔拉制了掺铈(Ce)光纤.通过X射线能谱(EDX)分析拉制而成的光纤,得到光纤的纤芯变为玻璃材料,而不再是晶体状态,这表明光纤拉制过程中芯棒与套管之间存在扩散现象.光纤在314nm光泵浦的情况下,产生约67nm (FWHM)光谱宽度的荧光辐射.     

适用于计算机绘图的数据结构浅议

计算机绘图中的数据处理,图学者往往感到棘手。本文介绍一种方便可行的数据结构,并举例说明其应用。     

基于二次B-B插值曲面的等值线图的绘制

介绍了基于二次 B- B插值曲面绘制等值线图的方法。实践表明 ,用这种方法绘制的等值线效果很好 ,它能有效地分析和解决工程问题     

面向总装的航天运载器三维数字化装配设计技术

对三维数字样机的技术现状进行了总结,归纳了传统二维总装图样的主要内容,分析以三维数字化总装出图代替二维总装图样的优势,提出三维数字化总装出图取代传统二维总装图样的技术方法,并对三维数字化总装出图的主要组成部分及表达形式进行阐述.     

A universal roll‐to‐roll slot‐die coating approach towards high‐efficiency organic photovoltaics

This work develops a combinational use of solvent additive and in‐line drying oven on the flexible organic photovoltaics to improve large‐area roll‐to‐roll (R2R) slot‐die coating process. Herein, addition of 1,8‐diiodooctane (DIO) in the photoactive layer is conducted to yield a performance of 3.05% based on the blending of poly(3‐hexylthiophene) (P3HT) and [6,6]‐phenyl C₆₁‐butyric acid methyl ester (PC₆₁BM), and a very promising device performance of 7.32% based on the blending of poly[[4,8‐bis[(2‐ethylhexyl)oxy] benzo[1,2‐b:4,5‐b’] dithiophene‐2,6‐diyl] [3‐fluoro‐2‐[(2‐ethylhexyl)carbonyl]thieno[3,4‐b]thiophenediyl]] (PTB7) and [6,6]‐phenyl C₇₁‐butyric acid methyl ester (PC₇₁BM). Based on this R2R slot‐die coating approach for various polymers, we demonstrate the high‐performance result with respect to the up‐scaling from small high‐PCE cell to large‐area module. This present study provides a route for fabricating a low‐cost, large‐area, and environmental‐friendly flexible organic photovoltaics.     

Customizing MRI-Compatible Multifunctional Neural Interfaces through Fiber Drawing

Fiber drawing enables scalable fabrication of multifunctional flexible fibers that integrate electrical, optical, and microfluidic modalities to record and modulate neural activity. Constraints on thermomechanical properties of materials, however, have prevented integrated drawing of metal electrodes with low-loss polymer waveguides for concurrent electrical recording and optical neuromodulation. Here, two fabrication approaches are introduced: 1) an iterative thermal drawing with a soft, low melting temperature (T_m) metal indium, and 2) a metal convergence drawing with traditionally non-drawable high T_m metal tungsten. Both approaches deliver multifunctional flexible neural interfaces with low-impedance metallic electrodes and low-loss waveguides, capable of recording optically-evoked and spontaneous neural activity in mice over several weeks. These fibers are coupled with a light-weight mechanical microdrive (1 g) that enables depth-specific interrogation of neural circuits in mice following chronic implantation. Finally, the compatibility of these fibers with magnetic resonance imaging is demonstrated and they are applied to visualize the delivery of chemical payloads through the integrated channels in real time. Together, these advances expand the domains of application of the fiber-based neural probes in neuroscience and neuroengineering.     

超高强度钢薄壁深盲孔弹体的精密成形技术

通过变形工序的合理安排以及变形程度的合理分配,设计合理的原始坯料形状,采用适宜的冷、温锻模具结构,获得了一种能够用于大批量工业生产的超高强度钢制薄壁深盲孔弹体的精密成形工艺,从而解决了其制造过程中的关键技术,为宇航、兵器等行业普遍采用的这类零件的生产提供了一种实用、高效、经济、可靠的精密成形工艺。     

Known Good Die

Advances in reducing size and increasing functionality of electronics have been due primarily to the shrinking geometries and increasing performance of integrated circuit technologies. Recently, development efforts aimed at reducing size and increasingfunctionality have focused on the first level of the electronicpackage. The result has been the development of multichip packaging,technologies in which bare IC chips are mounted on a single high density substrate that serves to package thechips, as well as interconnect them. A number of benefits accruebecause of multichip packaging, namely, increased chip density,space savings, higher performance, and less weight. Therefore, thesetechnologies are attractive for today's light weight, portable, highperformance electronic equipment and devices.In spite of these benefits, multichip packaging has not shown the kind of explosive growth and expansion that was predicted[1]. A major inhibitor for these technologies has been theavailability of fully tested and conditioned bare die, orknown good die. This paper reviews the issues and technologies associated with test and burn-in of bareor minimally packaged IC products.