蓝牙HCI-UART主控制接口的FPGA设计与实现

蓝牙技术作为一种短距离的无线通信技术,具有巨大的发展潜力,本文意从HCI层进行蓝牙技术的应用开发。本文首先介绍了HCI和UART的结构与原理,在分析和比较HCI三种类型接口USB、RS-232和UART优缺点的基础,提出了一种基于FPGA采用硬件设计HCI-UART的实现方式。本设计在QuartusII9.0集成设计环境下,采用硬件描述语言Verilog分模块设计完成,设计经过Modelsim6.4a仿真与验证。     

A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding

This report describes the design of a modular, massive-parallel, neural-network (NN)-based vector quantizer for real-time video coding. The NN is a self-organizing map (SOM) that works only in the training phase for codebook generation, only at the recall phase for real-time image coding, or in both phases for adaptive applications. The neural net can be learned using batch or adaptive training and is controlled by an inside circuit, finite-state machine-based hard controller. The SOM is described in VHDL and implemented on electrically (FPGA) and mask (standard-cell) programmable devices.     

Performance analysis challenges and framework for high-performance reconfigurable computing

Reconfigurable computing (RC) applications employing both microprocessors and FPGAs have potential for large speedup when compared with traditional (software) parallel applications. However, this potential is marred by the additional complexity of these dual-paradigm systems, making it difficult to identify performance bottlenecks and achieve desired performance. Performance analysis concepts and tools are well researched and widely available for traditional parallel applications but are lacking in RC, despite being of great importance due to the applications’ increased complexity. In this paper, we explore challenges and present new techniques in automated instrumentation, runtime measurement, and visualization of RC application behavior. We also present ideas for integration with conventional performance analysis tools to create a unified tool for RC applications as well as our initial framework for FPGA instrumentation and measurement. Results from a case study are provided using a prototype of this new tool.     

中性线有源滤波器重复学习控制及其数字算法实现

提出了一种新型中性线谐波治理装置,通过三个单相变压器的特殊连接方式,仅使用一个单相全桥逆变电路即可完成补偿要求,同时避免承受电网基波电压,有效降低开关损耗以及控制复杂程度;介绍了重复学习控制策略并给出其控制模型;最后使用FPGA和DSP给出了该控制的数字算法实现并研制了一套容量为10kVA的装置进行实验。     

FPGA按键模式的研究与设计

对FPGA设计中使用按键的常见方式进行归纳概括,提出单键复键两类共5种典型的按键模式:琴键、脉冲、乒乓、连发和长键模式,并对每种按键模式进行了分析与设计,同时给出了设计综合的仿真结果。     

数字信号处理的FPGA实现

介绍了三种常见的数字信号处理过程的FPGA实现,包括频率合成、AM调制和FM调制,并进行仿真和硬件下载验证。     

基于FPGA的IFFT处理器设计

通过分析FFT的Cooley-Tukey算法,导出相应的IFFT算法。采用Altera公司的Cyclone Ⅱ系列FPGA芯片中的FFT megacore IP核定制FFT功能,分别使用Quartus Ⅱ和VHDL开发工具验证实现。     

EMD 10G线路接口卡的硬件设计与实现

针对现有网络接入设备难以满足流媒体等新业务要求的问题,深入研究了EMD(扩展用分复用单元)10G线路接口卡的功能与结构,并针对上行数据流的合路问题提出了基于FPGA的WDRR(加权欠账轮询)算法,该算法在不过度改变计算复杂度的情况下,使得时延性能得到改善;针对超宽表项的1920位组播查表问题,提出了FPGA+TCAM+2~*SRAM的组播流水线查表,与传统的查表方案相比,其效率提高了67%。最后通过仿真,测试表明该硬件设计方案能够满足ACR路由器对EMD 10G线路接口卡的要求。     

数字电视CAS中DES加密模块的FPGA实现

一种基于 FPGA 的数据加密标准算法的实现。就资源优先和性能优先分别使用循环法和流水线法对 DES 加密算法进行了设计,并对其进行了比较。通过采用子密钥简单产生和 ROM 优化 S盒的方法,对流水线法进行改进,达到了资源占用率低、加密速度快的效果。     

基于FPGA控制的IDE磁盘阵列设计

设计了一种基于FPGA控制的高速数据存储系统。该系统采用FPGA实现了对四个符合ATA-6规范的、RAID0配置的IDE磁盘阵列的管理,并配合四个SDRAM实现对数据的高速稳定存储。该磁盘阵列同时挂四个IDE硬盘,平均数据流达到200MB/s,峰值传输速率达到800MB/s,也可以扩展更多硬盘,构成大容量的磁盘阵列。