基于混合宏模型的无电容型LDO设计

模拟集成电路的"自顶向下"设计方法能大大提高电路设计效率.提出了一种"混合宏模型",能高效、简便地完成模拟集成电路的建模,进而指导器件级电路设计.基于"混合宏模型"的设计方法,完成了一款基于HHNEC 0.25 μm标准CMOS工艺的无电容型LDO设计.     

2021年电子电路技术热点

文章归纳了2021年电子电路产业一些技术热点.鉴于电子电路的复杂化,印制电路板设计备受关注;鉴于印制电路板成本上升、竞争激烈,点点滴滴技术改进也值得重视.产业要持续发展,精细化新技术是技术热点.     

Design guidelines and comparison of detector readout front end integrated S-G shapers using transconductance circuits

An analysis of readout front end electronics semi-gaussian (S-G) shapers is carried out. Innovative design methodology is proposed and an advanced filter design technique based on operational transconductance amplifiers (OTA) is used, in order to implement fully integrated structures. Three respective novel CMOS shaper topologies are designed and compared in terms of noise performance, total harmonic distortion, dynamic range and power consumption as to examine which is the most preferable in readout applications. Analysis is supported by simulations results using SPICE in a 0.6?µm process by the Austria Mikro Systeme (AMS). The optimum implementation appears to be the OTA based cascade shaper structure with the inductor simulation. The specific shaper implementation is used in a fully integrated preamplifier-shaper system for a space application silicon strip detector of 2?pF capacitance. The readout system achieves an equivalent noise charge of 327 electrons at 1.7?µs peaking time in ?40°C.     

Active mode leakage reduction using fine-grained forward body biasing strategy

Leakage power minimization has become an important issue with technology scaling. Variable threshold voltage schemes have become popular for standby power reduction. In this work we look at another emerging aspect of this potent problem which is leakage power reduction in active mode of operation. In gate level circuits, a large number of gates are not switching in active mode at any given point in time but nevertheless are consuming leakage power. We propose a fine-grained forward body biasing (FBB) scheme for active mode leakage power reduction in gate level circuits without any delay penalty. Our results show that our optimal polynomial time FBB allocation algorithm results in 70.2% reduction in leakage currents. We also present an exact standard-cell placement driven FBB allocation algorithm that effectively reduces the area penalty using the post-placement area slack and results in 56.5%, 62.8% and 66.1% reduction in leakage currents for 0%, 4% and 8% area slack, respectively. Furthermore, we present a heuristic to solve the standard-cell placement driven FBB allocation problem that is computationally efficient and results in leakage within 2% of that from the exact formulation.     

设计文件标准化审查工作初探

介绍了设计文件标准化审查的内容，指出了存在的问题，并提出了解决的措施。     

Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO

Design optimization for performance enhancement in analog and mixed-signal circuits is an active area of research as technology scaling is moving towards the nanometer scale. This paper presents an approach towards the efficient simulation and characterization of mixed-signal circuits, using a 45 nm CMOS voltage controlled oscillator (VCO) with frequency divider as a case study. The performance characteristics of the analog and digital blocks in the circuit are simulated and the accuracy issues arising due to separate analog and digital simulation engines are considered. The tremendous impact of gate tunneling current on device performance is quantitatively analyzed with the help of an “effective tunneling capacitance”, which allows accurate modeling and simulation of digital blocks with almost analog accuracy. To meet the design specifications of the analog VCO using digital CMOS technology, we follow a design of experiments (DOE) approach. The functional specifications of the VCO optimized in this design are the center frequency and minimization of overall power consumption as well as minimization of power due to gate-oxide tunneling current leakage, a component that was not important in previous generations of CMOS technologies but is dominant at 45 nm and below. Due to the large number of available design parameter (gate-oxide thickness and transistor sizes), the concurrent achievement of all optimization goals is difficult. A DOE approach is shown to be very effective and a viable alternative to standard design exploration in the nanometer regime.     

Predictive Validity of an Empirical Approach for Selecting Promising Message Topics: A Randomized‐Controlled Study

Several message topic selection approaches propose that messages based on beliefs pretested and found to be more strongly associated with intentions will be more effective in changing population intentions and behaviors when used in a campaign. This study aimed to validate the underlying causal assumption of these approaches which rely on cross‐sectional belief–intention associations. We experimentally tested whether messages addressing promising themes as identified by the above criterion were more persuasive than messages addressing less promising themes. Contrary to expectations, all messages increased intentions. Interestingly, mediation analyses showed that while messages deemed promising affected intentions through changes in targeted promising beliefs, messages deemed less promising also achieved persuasion by influencing nontargeted promising beliefs. Implications for message topic selection are discussed.     

结合集成电路设计大赛谈创新能力的培养

科技大赛是推动大学生从事科技创新活动的重要途径,也是培养学生科技创新能力的重要手段。通过分析我国集成电路产业发展的现状及高校在创新人才培养方面存在的问题,介绍集成电路设计大赛在大学生实践创新能力培养方面的积极作用。     

A Mapping Framework Based on Packing for Design Space Exploration of Heterogeneous MPSoCs

The computational demand of signal processing algorithms is rising continuously. Heterogeneous embedded multiprocessor systems-on-chips are one solution to satisfy this demand. But to be able to take advantage of these systems, new strategies are required to map applications to such a system and to evaluate the systems performance at a very early design stage. We will present a framework for static, analytical, bottom-up temporal and spatial mapping of applications to MPSoCs based on packing. This mapping framework allows easy performance evaluation and design space exploration of heterogeneous systems on chip.

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a matrix band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.