Customizable hardware design of fuzzy controllers applied to autonomous car driving

Nowadays, final products often encompass a certain intelligence therein to deal with variation or lack of precision in the sensing input data. This intelligence is usually acquired via the utilization of existing soft techniques, such as artificial neural networks, genetic algorithms and fuzzy control, among others. Thus, it is profitable to have on-the-shelf shell scalable and adaptive hardware designs that implement these soft techniques. This availability allows for an immediate embedding of any of those designs onto final products. This usually entails a reduced time-to-market of the product. Process control is one of the many applications that took advantage of the fuzzy paradigm. In general, controllers are embedded into the controlled device. This paper presents a novel design of a reconfigurable efficient parallel architecture to implement fuzzy controllers on hardware with almost no design effort for final users. The proposed architecture is herein proven suitable for embedding. It is customizable, so it allows the setup and configuration of the controller parameters, and hence its use for any problem application. Two fuzzy controllers that model autonomous car driving are implemented and their cost and performance evaluated.     

主流视频编解码软件的硬件性能分析与设计

网络视频会议以及高清视频点播等应用的广泛流行,对视频编解码的编码质量以及编码速度提出了更高的要求。为帮助硬件设计人员设计更强大的专用处理器去适应视频编解码应用的发展趋势,并评估处理器设计的合理性和正确性,对视频编解码进行分析和测试,提出一套基准测试程序。采用自顶向下的分析方法,以流行性、编解码效率、压缩质量和开源性为标准,选取主流的视频编解码软件,进行热点函数分析。抽取变换、量化以及滤波过程中的热点函数,使之成为视频编解码测试程序,为其构造典型输入集。通过分析真实硬件平台上这些测试程序的计算和访存特性,给出处理器设计的建议。结果证明,该基准测试程序使用10%的代码量即可反映视频编解码过程的主要特征,对处理器设计具有指导意义。     

Prevention from Soft Errors via Architecture Elasticity

Due to the decreasing threshold voltages, shrinking feature size, as well as the exponential growth of on-chip transistors, modern processors are increasingly vulnerable to soft errors. However, traditional mechanisms of soft error mitigation take actions to deal with soft errors only after they have been detected. Instead of the passive responses, this paper proposes a novel mechanism which proactively prevents from the occurrence of soft errors via architecture elasticity. In the light of a predictive model, we adapt the processor architectures h01istically and dynamically. The predictive model provides the ability to quickly and accurately predict the simulation target across different program execution phases on any architecture configurations by leveraging an artificial neural network model. Experimental results on SPEC CPU 2000 benchmarks show that our method inherently reduces the soft error rate by 33.2% and improves the energy efficiency by 18.3% as compared with the static configuration processor.     

An Elastic Architecture Adaptable to Various Application Scenarios

The quantity of computer applications is increasing dramatically as the computer industry prospers. Meanwhile, even for one application, it has different requirements of performance and power in different scenarios. Although various processors with different architectures emerge to fit for the various applications in different scenarios, it is impossible to design a dedicated processor to meet all the requirements. Furthermore, dealing with uncertain processors significantly aggravates the burden of programmers and system integrators to achieve specific performance/power. In this paper, we propose elastic architecture （EA） to provide a uniform computing platform with high elasticity, i.e., the ratio of worst-case to best-case performance/power/performance-power trade-off, which can meet different requirements for different applications. It is achieved by dynamically adjusting architecture parameters （instruction set, branch predictor, data path, memory hierarchy, concurrency, status~zcontrol, and so on） on demand. The elasticity of our prototype implementation of EA, as Sim-EA, ranges from 3.31 to 14.34, with 5.41 in arithmetic average, for SPEC CPU2000 benchmark suites, which provides great flexibility to fulfill the different performance and power requirements in different scenarios. Moreover, Sim-EA can reduce the EDP （energy-delay product） for 31.14% in arithmetic average compared with a baseline fixed architecture. Besides, some subsequent experiments indicate a negative correlation between application intervals＇ lengths and their elasticities.     

一种新型指纹锁电路设计

市场上主流的电子锁是基于密码设计的。密码锁的最大的缺陷是密码容易被他人窃取、猜测及遗忘。随着生物技术的发展,越来越多的活体技术应用到识别系统中,如指纹、掌纹、人脸、虹膜等。相对于其它的活体识别技术,指纹识别系统以其可实现性强,成本相对低廉,同时又具备较高的安全性,被越来越多的应用到各种场合。文章给出了一种新型的指纹锁架构,并详细论述了系统的各个组成部分以及指纹识别算法的实现流程。文章对降低系统功耗和增加保密性都提出了独特的方法。     

气象传感器网络系统架构与体系结构研究

传感器网络将在气象观测领域发挥越来越重要的作用。针对地面气象观测的现实需求,提出了气象传感器网络的概念,构建了气象传感器网络的应用场景,完成了其需求分析与系统架构设计,深入分析了气象传感器网络可采用的通信手段。在陆上传感器网络体系结构的基础上,结合气象传感器网络的特点,设计了气象传感器网络的体系结构,将其结构划分为物理层、数据链路层和网络层。对该体系结构各层的功能进行了深入分析,最后对气象传感器网络的应用前景进行了展望。     

广西古代陶器组成的研究

桂林甑皮岩遗址发现了距今９２４０－１０３７０年的陶片，证实了广西地区从新石器以来就成为我国古代陶器的发源地之一。本工作研究了广西出土的４４块陶片，测定了陶胎的化学和矿物组成。由此表面广西古陶的ＳｉＯ２含量随时代变迁而逐渐增加，而Ｆｅ２Ｏ３含量在明显下降，Ａｌ２Ｏ３的含量也有降低的趋势。     

An exploratory study on ontology engineering for software architecture documentation

The usefulness of Software Architecture (SA) documentation depends on how well its Architectural Knowledge (AK) can be retrieved by the stakeholders in a software project. Recent findings show that the use of ontology-based SA documentation is promising. However, different roles in software development have different needs for AK, and building an ontology to suit these needs is challenging. In this paper we describe an approach to build an ontology for SA documentation. This approach involves the use of typical questions for eliciting and constructing an ontology. We outline eight contextual factors, which influence the successful construction of an ontology, especially in complex software projects with diverse AK users. We tested our ‘typical question’ approach in a case study and report how it can be used for acquiring and modeling AK needs.     

Using the cloud to develop applications supporting geo-collaborative Situated Learning

Situated Learning stresses the importance of the context in which learning takes place. It has been therefore frequently associated with informal learning or learning outside the classroom. Cloud technologies can play an important role supporting this type of learning, since it requires ubiquitous computing support, connectivity and access to data across various scenarios: on the field, in the classroom, at home, etc. In this paper we first present the situated learning theory and how we can take advantage of services offered by Cloud Computing to implement computer applications implementing learning activities based on this theory, providing pertinent geographical information and discussion boards. Next we propose a software architecture schema which can be used as a basis for integrating existing cloud services into new applications supporting learning activities. Then we present two examples developed with this approach with its viability and advantages. These are discussed in the concluding chapter.     

FPGA prototyping of emerging manycore architectures for parallel programming research using Formic boards

Performance evaluation of parallel software and architectural exploration of innovative hardware support face a common challenge with emerging manycore platforms: they are limited by the slow running time and the low accuracy of software simulators. Manycore FPGA prototypes are difficult to build, but they offer great rewards. Software running on such prototypes runs orders of magnitude faster than current simulators. Moreover, researchers gain significant architectural insight during the modeling process. We use the Formic FPGA prototyping board [1], which specifically targets scalable and cost-efficient multi-board prototyping, to build and test a 64-board model of a 512-core, MicroBlaze-based, non-coherent hardware prototype with a full network-on-chip in a 3D-mesh topology. We expand the hardware architecture to include the ARM Versatile Express platforms and build a 520-core heterogeneous prototype of 8 Cortex-A9 cores and 512 MicroBlaze cores. We then develop an MPI library for the prototype and evaluate it extensively using several bare-metal and MPI benchmarks. We find that our processor prototype is highly scalable, models faithfully single-chip multicore architectures, and is a very efficient platform for parallel programming research, being 50,000 times faster than software simulation.