Mitigating the gateway bottleneck via transparent cooperative caching in wireless mesh networks

Wireless mesh networks (WMNs) have been proposed to provide cheap, easily deployable and robust Internet access. The dominant Internet-access traffic from clients causes a congestion bottleneck around the gateway, which can significantly limit the throughput of the WMN clients in accessing the Internet. In this paper, we present MeshCache, a transparent caching system for WMNs that exploits the locality in client Internet-access traffic to mitigate the bottleneck effect at the gateway, thereby improving client-perceived performance. MeshCache leverages the fact that a WMN typically spans a small geographic area and hence mesh routers are easily over-provisioned with CPU, memory, and disk storage, and extends the individual wireless mesh routers in a WMN with built-in content caching functionality. It then performs cooperative caching among the wireless mesh routers.We explore two architecture designs for MeshCache: (1) caching at every client access mesh router upon file download, and (2) caching at each mesh router along the route the Internet-access traffic travels, which requires breaking a single end-to-end transport connection into multiple single-hop transport connections along the route. We also leverage the abundant research results from cooperative web caching in the Internet in designing cache selection protocols for efficiently locating caches containing data objects for these two architectures. We further compare these two MeshCache designs with caching at the gateway router only.Through extensive simulations and evaluations using a prototype implementation on a testbed, we find that MeshCache can significantly improve the performance of client nodes in WMNs. In particular, our experiments with a Squid-based MeshCache implementation deployed on the MAP mesh network testbed with 15 routers show that compared to caching at the gateway only, the MeshCache architecture with hop-by-hop caching reduces the load at the gateway by 38%, improves the average client throughput by 170%, and increases the number of transfers that achieve a throughput greater than 1 Mbps by a factor of 3.     

基于流媒体技术的开放型实验教学体系框架的思考

为探索实验室彻底开放的长效运行机制及适应开放教学的实验教学条件,同时为帮助学生集中梳理所学知识,融会贯通地学习,本文提出以流媒体技术为支撑把验证性实验教学环节交由视频演示和研究生助教辅助指导,并在实验室里以视频方式完全展现出一个学科体系的知识架构从而改变基础验证性实验教学环节中学和教的机制,做到实验教学资源视频化、网络化、图书馆化、共享化、并向全社会辐射、同时还探索了实验室建设经费来源多样化问题。     

Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

基于有限状态机的QPSK调制系统发送模块FPGA实现

分析了所设计的通信系统发射波形的帧格式,结合有限状态机（Finite State Machine,FS M）的设计思想,在FPGA上实现了通信系统的发送模块,将同步头数据、标志位数据 、相位校正数据、正文数据各部分数据按先后顺序有序发送,实现了模块间的无缝链接,使 系统的数据发送稳定可靠。     

RKR-GST算法在.NET中的分析与实现

针对计算字符串相似度的RKR-GST算法,分析了与该算法相关的技术并给出算法的流程图,然后在Visual Studio 2008中对该算法进行了实现,详细描述了实现过程中涉及的类与数据结构图,最后对算法的复杂度及算法运行过程中一些参数的选取进行了讨论。RKR-GST算法在剽窃检测、DNA序列匹配等领域具有广阔的应用前景,该算法在.NET中的实现具有良好的可移植性与可扩展性,可以在多个应用领域中推广使用。     

Circuit Design of On-Chip BP Learning Neural Network with Programmable Neuron Characteristics

A circuit system of on chip BP(Back-Propagation) learning neural network with pro grammable neurons has been designed,which comprises a feedforward network,an error backpropagation network and a weight updating circuit. It has the merits of simplicity,programmability, speedness,low power-consumption and high density. A novel neuron circuit with pro grammable parameters has been proposed. It generates not only the sigmoidal function but also its derivative. HSPICE simulations are done to a neuron circuit with level 47 transistor models as a standard 1.2tμm CMOS process. The results show that both functions are matched with their respec ive ideal functions very well. The non-linear partition problem is used to verify the operation of the network. The simulation result shows the superior performance of this BP neural network with on-chip learning.     

星载电子侦察中的新型宽带DBF测向技术

针对星载电子侦察系统体积小、重量轻、功耗低和实时处理的要求,提出了一种新型宽带DBF测向技术。与其它DBF测向技术相比,该技术在保证了较高测向精度的前提下,具有算法简单、可并行处理、易于硬件实现和可实时处理的特点,因此非常适合于星载电子侦察应用。     

椭圆曲线密码处理器的高效VLSI设计与实现

采用复合武硬件设计方法，通过数学公式推导和电路结构设计，完成了一款GF（2m）域椭圆曲线密码处理器的高效VLSI实现。以低成本为目标，对算术逻辑模块的乘法、约减、平方、求逆，以及控制电路模块都进行了优化设计。按照椭圆曲线密码的不同运算层次，设计了不同层次的控制电路。该处理器综合在中芯国际SMIC0．18μm标准工艺库上．比相关研究的芯片面积节省48％，同时保证了很快的速度。