封装中的界面热应力分析

随着电子封装集成度的不断提高,集成电路的功率容量和发热量也越来越高,封装体内就产生了越来越多的温度分布以及热应力问题。文章建立了基板-粘结层-硅芯片热应力分析有限元模型,利用有限元法分析了芯片/基板的热应力分布,封装体的几何结构参数对应力的影响,重点讨论了芯片与粘结层界面上和基板与粘结层界面上的层间应力分布     

毫米波系统级封装中的基板功能化实现

阐述了毫米波系统级封装（SOP）架构中基板功能化的概念、作用及实现方法。提出了利用低温共烧陶瓷（LTCC）技术,在SOP多层陶瓷基板中一体化集成多种无源电路单元,使封装基板在作为表面贴装有源芯片载体的同时,自身具备相应的无源射频功能。最终通过设计实例的仿真、加工及测试对比,验证了在SOP架构下实现封装基板功能化的可行性,及其所具有的良好的射频滤波、层间信号互联、射频接口过渡等电气性能。     

Fabrication of extremely thermal-stable GaN template on Mo substrate using double bonding and step annealing process

A new layer transfer technique which comprised double bonding and a step annealing process was utilized to transfer the GaN epilayer from a sapphire substrate to a Mo substrate. Combined with the application of the thermal-stable bonding medium, the resulting two-inch-diameter GaN template showed extremely good stability under high temperature and low stress state. Moreover, no cracks and winkles were observed. The transferred GaN template was suitable for homogeneous epitaxial, thus could be used for the direct fabrication of vertical LED chips as well as power electron devices. It has been confirmed that the double bonding and step annealing technique together with the thermal-stable bonding layer could significantly improve the bonding strength and stress relief, finally enhancing the thermal stability of the transferred GaN template.     

一种毫米波BGA封装低成本测试方法

提出一种可应用于毫米波BGA(Ball Grid Array)封装器件的低成本无损测试方法.该测试方案主要由毛纽扣及两块单层基板组成.其中,毛纽扣作为封装焊球与基板之间的垂直互联媒介,实现信号传输.同时,毛纽扣具有较小的弹性接触力,在测试过程中能够保护焊球不受损伤.毛纽扣与基板形成的介质填充类同轴结构和基板上的高低阻抗...     

微波组件用镀镍壳体的烧结性能研究

用荧光厚度分析仪、X光透视、扫描电子显微镜/能谱仪及切片分析等手段研究了不同镀镍壳体的烧结性能。结果表明,不同镀镍类型的镀层可焊性不同,电镀暗镍可焊性最差,电镀氨基磺酸镍和化学镀NiP的可焊性相对较好。SnAgCu焊料与镀镍壳体润湿较好,基片烧结空洞率较低,烧结界面与壳体及基片和玻璃绝缘子结合致密,玻璃绝缘子烧结的密封检漏通过率达90%。温度冲击后,烧结界面无明显分层和裂纹出现,镀镍壳体试制样品的电性能满足设计要求。     

Layout Design and Optimization of RF Spiral Inductors on Silicon Substrate

使用三维电磁场模拟的方法对相同硅衬底结构下不同布图结构的螺旋电感进行了模拟和分析.通过改变电感匝数、电感金属的宽度和间隔以及电感的内径,模拟和分析了电感性能的变化.给出了引起电感性能变化的原因.结果表明优化电感的几何参数可以有效地改善电感性能.得出了一些实用的设计原则,可有效地指导射频集成电路中集成电感的设计.     

Adaptation of Oxidative Phosphorylation Machinery Compensates for Hepatic Lipotoxicity in Early Stages of MAFLD

Alterations in mitochondrial function are an important control variable in the progression of metabolic dysfunction-associated fatty liver disease (MAFLD), while also noted by increased de novo lipogenesis (DNL) and hepatic insulin resistance. We hypothesized that the organization and function of a mitochondrial electron transport chain (ETC) in this pathologic condition is a consequence of shifted substrate availability. We addressed this question using a transgenic mouse model with increased hepatic insulin resistance and DNL due to constitutively active human SREBP-1c. The abundance of ETC complex subunits and components of key metabolic pathways are regulated in the liver of these animals. Further omics approaches combined with functional assays in isolated liver mitochondria and primary hepatocytes revealed that the SREBP-1c-forced fatty liver induced a substrate limitation for oxidative phosphorylation, inducing enhanced complex II activity. The observed increased expression of mitochondrial genes may have indicated a counteraction. In conclusion, a shift of available substrates directed toward activated DNL results in increased electron flows, mainly through complex II, to compensate for the increased energy demand of the cell. The reorganization of key compounds in energy metabolism observed in the SREBP-1c animal model might explain the initial increase in mitochondrial function observed in the early stages of human MAFLD.     

低翘曲度ITO透明导电膜玻璃的工艺研究

研究了不同厚度ITO膜的大尺寸超薄导电玻璃的翘曲度,ITO膜形成期间基片温度对ITO膜层晶体化程度的影响及不同基片温度下形成的ITO膜层在不同的退火条件下的退火前、后的电阻率和膜压应力.实验发现,ITO膜层的很高的压应力是导致导电膜玻璃翘曲的直接原因;采用室温沉积非晶ITO膜,然后经高温热退火可获得低膜压应力多晶相ITO膜.基于实验结论,提出了一种适合批量生产的低翘曲度ITO膜导电玻璃的制备工艺.     

Role of interfacial-charge in the growth of GaN on α-SiC

The growth of GaN and A1N films on (0001) substrates of 6H-SiC has produced high-quality opto-electronic films. The SiC surface at the interface with GaN or A1N is either Si-terminated or C-terminated, and the Si-terminated interface is known to be the better substrate, producing higher-quality films. The polarity of the interface is important, as recognized by Sasaki and Matsuoka. We propose that the main relevant parameter for characterizing the interface and its potential for producing high-quality opto-electronic GaN or A1N films is the interfacial charge, which leads to the best films when the charge is positive and relatively large. The positive charge reduces the size of the Nions at the interface and hence improves the local lattice match. (The charges are approximately −0.45 lei and +0.55 lei on the interfacial N and Si atoms, respectively.) Therefore, while the polarity of the interface is important, the polarity's effect on the local lattice mismatch is what leads to a high-quality interface. These ideas are consistent with XPS data and are supported by electronegativity arguments, by calculations for ordinary mono-bonded GaN/SiC superlattices (with N-Si and Ga-C interfaces) and by computations for superlattices with tri-bonded interfaces. We predict that the tri-bonded N-Si interface of GaN/SiC should produce excellent GaN and AIN films.     

pMOSFET中栅控产生电流的衬底偏压影响研究

研究了pMOSFET中栅控产生电流(GD)的衬底偏压特性。衬底施加负偏压后,GD电流峰值变小;衬底加正向偏压后,GD电流峰值增大。这归因于衬底偏压VB调制了MOSFET的栅控产生电流中最大产生率,并求出了衬底偏压作用系数为0.3。考虑VB对漏PN结的作用,建立了包含衬底偏压的产生电流模型。基于该模型的深入分析,很好地解释了衬底负偏压比衬底正偏压对产生电流的影响大的实验结果。