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排序方式: 共有1151条查询结果,搜索用时 125 毫秒
1.
用CPLD实现SRAM工艺FPGA的安全应用 总被引:1,自引:0,他引:1
提出了一种利用CPLD产生的伪随机码来加密SRAM工艺FPGA的方法,并详细介绍了具体的电路和VHDL代码。 相似文献
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This paper describes the implementation of a stereo-vision system using Field Programmable Gate Arrays (FPGAs). Reconfigurable hardware, including FPGAs, is an attractive platform for implementing vision algorithms due to its ability to exploit parallelism often found in these algorithms, and due to the speed with which applications can be developed as compared to hardware. The system outputs 8-bit, subpixel disparity estimates for 256× 360 pixel images at 30,fps. A local-weighted phase correlation algorithm for stereo disparity [Fleet, D. J.: {Int. Conf. Syst. Man Cybernetics 1:48–54 (1994)] is implemented. Despite the complexity of performing correlations on multiscale, multiorientation phase data, the system runs as much as 300 times faster in hardware than its software implementation. This paper describes the hardware platform used, the algorithm, and the issues encountered during its hardware implementation. Of particular interest is the implementation of multiscale, steerable filters, which are widely used in computer vision algorithms. Several trade-offs (reducing the number of filter orientations from three to two, using fixed-point computation, changing the location of one localized low-pass filter, and using L1 instead of L2 norms) were required to both fit the design into the available hardware and to achieve video-rate processing. Finally, results from the system are given both for synthetic data sets as well as several standard stereo-pair test images. 相似文献
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High-k材料是指介电常数k高于SiO2的材料。使用high-k材料做栅绝缘层,是减小MOS器件栅绝缘层直接隧道击穿(DirectTunneling,DT)电流的有效方法。文章在二维器件模拟软件PISCES-II中添加了模拟以high-k材料为栅绝缘层的MOS器件模型,并对SiO2和high-k材料的MOS晶体管器件特性进行了模拟比较,成功地验证了所加high-k材料MOS器件模型的正确性。改进后的PISCES-II程序,可以方便地对以各种high-k材料为栅绝缘层的器件性能进行模拟。 相似文献
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针对图形处理器三维引擎中对图形的后期处理需求,实现片段写入帧缓冲区前的测试、混合、逻辑操作、累积、清除和屏蔽等关键功能。分析并提取了OpenGL核心库中的片段处理相关函数,确定了片段处理单元要实现的功能;合理安排多个片段处理功能的执行顺序,设计了基于流水线的片段处理单元结构;采用Verilog HDL对电路进行描述,采用 Cadence NC-Verilog 仿真工具进行虚拟验证,采用 Xilinx 的 ISE 工具进行综合,并在 Xilinx Virtex6 XC6VLX760 FPGA上进行原型验证,电路工作频率可以达到180 MHz,测试功能正确。在SMIC 65 nm CMOS工艺下,采用Synopsys Design-Compiler对设计进行综合,电路工作频率达到300 MHz,满足设计需求。 相似文献
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将数值模拟技术和优化算法相结合,提出了基于数值模拟技术的浇口位置的优化方法:经验搜索法。并对浇口位置与塑件质量关系进行了分析和总结,归纳出浇口位置设计的基本原则,提出了确定各类塑件浇口位置的具体准则。通过算例分析和方案比较,证明所提出的优化方法是行之有效的。 相似文献
9.
本文对反应注射充模过程中的铺展流、射流、绕流和气泡的特性进行了分析研究,并讨论了模具浇口结构及位置对充模的影响,给出了制品的设计方法。 相似文献
10.
Gate location design in injection molding of an automobile junction box with integral hinges 总被引:5,自引:0,他引:5
Polymers such as polypropylene or polyethylene offer a unique feature of producing an integral or living hinge for automobiles, which can flex over a million times without causing a failure. However, due to increased fluidity resistance at hinges during molding, several defects such as short shot or premature failure can occur with the improper selection of gate locations. In this paper, a design guideline was induced by investigating resin flow patterns depending on several gate positions obtained by numerical analyses of a simple strip with a hinge. The analyses of the simple strip part showed that the resin at the hinge did not flow until the other side of the strip was filled. Once the resin at the hinge did not flow for a long time enough to be solidified, defects such as short shots or hesitation marks formed. For a practical application of the design guideline determined, four gate systems for an automobile junction box were designed. It was found that the properly determined gate location leads to better resin flow and shorter hesitation time. Finally, injection molding tryouts using a mold that was designed by one of the proposed gate systems were conducted. The experiments showed that hinges without defects could be produced by using the designed gate location to assure the induced design guideline to be reasonable. 相似文献