Optimal gate sizing using a self-tuning multi-objective framework

In this paper, we present a self-tuning multi-objective framework for geometric programming that provides a fine trade-off between the competing objectives. The significance of this framework is that the designer does not need to perform any tuning of weights of objectives. The proposed framework is applied to gate sizing and clock network buffer sizing problems. In gate sizing application, power consumption is reduced on average by 86% while delay sees only an increase of 34 ns. In clock network butter sizing application, our framework results in a significant reduction in power, 57%, and an improvement of 31 ps in skew.     

Timing slack optimization approach using FPGA hybrid routing strategy of rip-up-retry and pathfinder

To improve the path slack of Field Programmable Gate Array （FPGA）, this paper proposes a timing slack optimization approach which utilizes the hybrid routing strategy of rip-up-retry and pathfinder. Firstly, effect of process variations on path slack is analyzed, and by constructing a col- location table of delay model that takes into account the multi-corner process, the complex statistical static timing analysis is successfully translated into a simple classical static timing analysis. Then, based on the hybrid routing strategy of rip-up-retry and pathfinder, by adjusting the critical path which detours a long distance, the critical path delay is reduced and the path slack is optimized. Experimental results show that, using the hybrid routing strategy, the number of paths with negative slack can be optimized （reduced） by 85.8% on average compared with the Versatile Place and Route （VPR） tim- ing-driven routing algorithm, while the run-time is only increased by 15.02% on average.     

Solution processable bilayered gate dielectric towards flexible organic thin film transistors

In this study, we have successfully explored the potential of a new bilayer gate dielectric material, composed of Polystyrene (PS), Pluronic P123 Block Copolymer Surfactant (P123) composite thin film and Polyacrylonitrile (PAN) through fabrication of metal insulator metal (MIM) capacitor devices and organic thin film transistors (OTFTs). The conditions for fabrication of PAN and PS-P123 as a bilayer dielectric material are optimized before employing it further as a gate dielectric in OTFTs. Simple solution processable techniques are applied to deposit PAN and PS-P123 as a bilayer dielectric layer on Polyimide (PI) substrates. Contact angle study is further performed to explore the surface property of this bilayer polymer gate dielectric material. This new bilayer dielectric having a k value of 3.7 intermediate to that of PS-P123 composite thin film dielectric (k ∼ 2.8) and PAN dielectric (k ∼ 5.5) has successfully acted as a buffer layer by preventing the direct contact between the organic semiconducting layer and high k PAN dielectric. The OTFT devices based on α,ω-dihexylquaterthiophene (DH4T) incorporated with this bilayer dielectric, has demonstrated a hole mobility of 1.37 × 10⁻² and on/off current ratio of 10³ which is one of the good values as reported before. Several bending conditions are applied, to explore the charge carrier hopping mechanism involved in deterioration of electrical properties of these OTFTs. Additionally, the electrical performance of OTFTs, which are exposed to open atmosphere for five days, can be interestingly recovered by means of re-baking them respectively at 90 °C.     

Surface states related the bias stability of amorphous In–Ga–Zn–O thin film transistors under different ambient gasses

This paper investigates the origin of the bias stability under ambient gas (oxygen, moisture and vacuum) of In–Ga–Zn–O thin film transistors with different annealing temperatures. In Zn-based TFTs, the electrical characteristic of device is a strongly function with the ambient gas, the simultaneous gas ambient and bias stresses are applied on devices annealed in atmosphere ambient to study this issue. The result shows the device which is annealed at temperature up to 330 °C has worst reliability. We suppose that the sensitivity of gas ambient depend the defect state, which is associated to the annealing temperature, of surface in a-IGZO.     

Enhancement of the electrical characteristics of MOS capacitors by reducing the organic content of H2O-diluted Spin-On-Glass based oxides

In this work, the physical, chemical and electrical properties of Metal-Oxide-Semiconductor (MOS) capacitors with Spin-On-Glass (SOG)-based thin films as gate dielectric have been investigated. Experiments of SOG diluted with two different solvents (2-propanol and deionized water) were done in order to reduce the viscosity of the SOG solution so that thinner films (down to ∼20 nm) could be obtained and their general characteristics compared. Thin films of SOG were deposited on silicon by the sol-gel technique and they were thermally annealed using conventional oxidation furnace and Rapid Thermal Processing (RTP) systems within N₂ ambient after deposition. SOG dilution using non-organic solvents like deionized water and further annealing (at relatively high temperatures ≥450 °C) are important processes intended to reduce the organic content of the films. Fourier-Transform Infrared (FTIR) Spectroscopy results have shown that water-diluted SOG films have a significant reduction in their organic content after increasing annealing temperature and/or dilution percentage when compared to those of undiluted SOG films. Both current-voltage (I-V) and capacitance-voltage (C-V) measurements show better electrical characteristics for SOG-films diluted in deionized water compared to those diluted in 2-propanol (which is an organic solvent). The electrical characteristics of H₂O-diluted SOG thin films are very similar to those obtained from high quality thermal oxides so that their application as gate dielectrics in MOS devices is promising. Finally, it has been demonstrated that by reducing the organic content of SOG-based thin films, it is possible to obtain MOS devices with better electrical properties.     

基于FPGA的千兆以太网协议分析技术

该文主要阐述在FPGA（Field—Programmable Gate Array）内千兆以太网协议数据流帧的生成、编码、组帧、解帧及协议帧分析,详细地阐述了BCM5421和FPGA组合的硬件设计技术、协议发生的FPGA设计技术、协议解码、过滤、性能分析的FPGA设计技术等关键技术的实现途径。     

RS(31,27)高速编译码器的FPGA实现

RS码是目前最有效、应用最广泛的差错控制编码方法之一.该文深入研究了RS编解码的原理,对相关算法进行优化.并在FPGA上实现了(31,27)编解码器.由仿真结果验证了该编解码器占用系统资源少,运行时间快,能够满足通信系统上的要求.     

基于SOPC的雷达嵌入式温控系统设计

为了解决某型雷达中的温控难题,提出了一种基于FPGA和可编程片上系统(SOPC)的雷达分布式温控系统。阐述了温控系统的组成、SOPC系统的搭建、外围接口电路设计以及μC/OS-II嵌入式操作系统下的软件设计。该系统采用SOPC技术搭建Nios II软核处理器,对单总线上的温度传感器进行采集,然后通过网络通信将温度数据上传至上位机,极大地提升了系统的集成度,简化了设备接口,且易于扩展,提高了电磁兼容性。     

低热梯度导向的三维FPGA互连通道网络架构研究

该文针对3维FPGA (3D FPGA)芯片存在的散热问题,提出具有低热梯度特征的互连网络通道结构,力图解决传统FPGA匀称互连通道设计在芯片堆叠实现上产生的温度非平衡现象。该文建立了3D FPGA的热阻网络模型;对不同类型的通道线对3D FPGA的热分布影响进行了理论分析和热仿真;提出了垂直方向通道网络非均匀分布的3D FPGA通道结构,实验表明,与给定传统FPGA互连通道结构相比,采用所提方法实现的3D FPGA设计架构能够降低76.8%的层间最高温度梯度,10.4%的层内温度梯度。     

滑模技术在某电站闸门井混凝土施工中的应用

某电站闸门井深达43m,如果采用常规混凝土施工方法,时间长、成本高,难以满足工期要求.经比较选择,该电站闸门井的浇筑采用滑模技术,确保了施工进度,施工质量较好,同时相对常规施工方法大大节约成本。