Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.     

数字电路的计算机仿真

用一种既不需要设备，又行之有效的方法来验证一个数字电路的正确性和有效性，这是设计人员所希望的。这篇文章正是为解决前述问题所给出的一个仿真器。该仿真器根据电路中各结点状态之间的逻辑关系来模拟电路的工作过程；它是一个实用化的应用程序，包括对电路的仿真及输出的格式、形式(真值形式或波形形式)等。     

基于FPGA的RapidIO核接口芯片的设计和实现

新型嵌入式系统采用基于交叉开关的互连模式，用于系统互连的交叉开关是以RapidIO协议为核心的。RapidIO协议是一个点对点、包交换的协议。通过对RapidIO协议的研究，掌握了实现该协议的关键技术。使用Xilinx公司的FPGA(可编程门阵列)芯片实现基于RapidIO核的终端设备，并通过软件仿真和硬件实验系统对其功能进行验证。     

Ultraviolet photoresponse of ZnO nanostructured AlGaN/GaN HEMTs

We present the first active visible blind ultraviolet (UV) photodetector based on zinc oxide (ZnO) nanostructured AlGaN/GaN high electron mobility transistors (HEMTs). The ZnO nanorods (NRs) are selectively grown on the gate area by using hydrothermal method. It is shown that ZnO nanorod (NR)-gated UV detectors exhibit much superior performance in terms of response speed and recovery time to those of seed-layer-gated detectors. It is also found that the best response speed (~10 and~190 ms) and responsivity (~1.1×10⁵ A/W) were observed from detectors of the shortest gate length of 2 µm among our NR-gated devices of three different gate dimensions, and this responsivity is about one order higher than the best performance of ZnO NR-based UV detectors reported to date.     

Crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors

In this paper, we report on the fabrication of a crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors (TFTs). We used cyanoethylated pullulan (CEP) as a crosslinkable high-k polymer matrix and poly(ethylene-alt-maleic anhydride) (PEMA) as a polymeric crosslinking agent. Because PEMA has a high number of functional groups reactive to the hydroxyl groups of CEP, the use of PEMA is effective for minimizing the amount of remaining hydroxyl groups strongly related to the large current hysteresis and high off current of the organic TFTs. To investigate the potential of the CEP-PEMA mixture as a gate insulator, we fabricated 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C₈-BTBT) TFTs. The C₈-BTBT TFT with the 60 nm-thick CEP-PEMA gate insulator showed excellent TFT performance with a field-effect mobility of 1.4 cm²/V s and an on/off ratio of 2.4 × 10⁶.     

Breakout local search for the multi-objective gate allocation problem

The problem of assigning gates to arriving and departing flights is one of the most important problems in airport operations. We take into account the real multi-criteria nature of the problem by optimizing a total of nine gate allocation objectives that are oriented both on convenience for airport/airline services and passenger comfort. As far as we are aware, this is the largest number of objectives jointly optimized in the GAP literature. Given the complexity of the considered problem, we propose a heuristic approach based on the Breakout Local Search (BLS) framework. BLS is a recent variant of the Iterated Local Search (ILS) with a particular focus on the perturbation strategy. Based on some relevant information on search history, it tries to introduce an appropriate degree of diversification by determining adaptively the number and type of moves for the next perturbation phase. Moreover, we use a new memory-based greedy constructive heuristic to generate a starting point for BLS. Benchmark instances used for our experiments and comparisons are based on information provided by Manchester Airport.     

A nature-inspired firefly algorithm based approach for nanoscale leakage optimal RTL structure

Optimization of leakage power is essential for nanoscale CMOS (nano-CMOS) technology based integrated circuits for numerous reasons, including improving battery life of the system in which they are used as well as enhancing reliability. Leakage optimization at an early stage of the design cycle such as the register-transfer level (RTL) or architectural level provides more degrees of freedom to design engineers and ensures that the design is optimized at higher levels before proceeding to the next and more detailed phases of the design cycle. In this paper, an RTL optimization approach is presented that targets leakage-power optimization while performing simultaneous scheduling, allocation and binding. The optimization approach uses a nature-inspired firefly algorithm so that large digital integrated circuits can be effectively handled without convergence issues. The firefly algorithm optimizes the cost of leakage delay product (LDP) under various resource constraints. As a specific example, gate-oxide leakage is optimized using a 45 nm CMOS dual-oxide based pre-characterized datapath library. Experimental results over various architectural level benchmark integrated circuits show that average leakage optimization of 90% can be obtained. For a comparative perspective, an integer linear programming (ILP) based algorithm is also presented and it is observed that the firefly algorithm is as accurate as ILP while converging much faster. To the best of the authors׳ knowledge, this is the first ever paper that applies firefly based algorithms for RTL optimization.     

Investigation of geometry dependence on MOSFET linearity in the impact ionization region using Volterra series

In this paper, investigation of device geometry on intermodulation distortion (IMD) of metal–oxide–semiconductor field-effect transistors (MOSFETs) is presented in the impact ionization region based on the Volterra analysis. As the gate length or gate width decreases, observed linearity improvement of the MOSFET in the breakdown regime is attributed to the more obvious breakdown inductance nonlinearity which cancels the transconductance nonlinearity. Linearity of the MOSFETs can be improved by choosing suitable device geometry in the breakdown region. It is believed the presented analysis results can benefit the reliability investigation for MOSFET linearity in the breakdown region.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

裸眼3D系统SD卡FPGA读取显示研究

SD卡可为便携式裸眼3D设备提供数据来源,图像存储于SD卡中,FPGA以SPI协议方式读出,再经过FIFO和SDRAM进行数据缓存,通过接口输入显示器显示.探讨了通过FPGA器件读取SD卡图像进行显示的实现方法,得出了SD卡文件读取及显示的可行逻辑设计.系统性能经过初步验证,可行性良好.