可编程增益多通道数据采集系统研究

本文提出了一种利用现场可编程门阵列（FPGA）、仪表运算放大器AD623和高精度AD转换器实现多通道数据数据采集系统的原理.通过对FPGA进行编程配置,可以对不同通道输入的伏值不同的电压信号分别设置增益,使每一个通道输出的信号正好在AD采集所需要的信号范围内,满足了采集要求.实验结果表明该设计结构简单、体积小、适用性强、性能优良、可控性好、能够满足大部分试验和科研过程的需求,具有很广泛的适用性.     

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

模拟电路在线故障检测与诊断的FPGA实现

选择节点电压、幅频特性和相频特性构成故障特征向量集,并根据多通道宽带数据采集接口和驱动程序,给出全数字式的正交幅相特性实时检测方法。利用网络分析与信息融合技术,设计一种模拟电路在线检测和诊断方案,并在现场可编程门阵列硬件系统中进行实现,以解决诸多模拟电路故障诊断算法缺乏测试平台而停留在仿真阶段的问题。实例分析结果表明,该系统可有效识别电路软故障,在存在元件容差的情况下,其识别准确率高达96％,时间消耗低于60ms。     

基于 RFID-SIM 的小区无线门禁系统

针对现代小区各种智能管理系统需要多种智能卡识别给用户带来使用不便、信息不能共享等问题,结合射频识别技术、SIM 技术和 ZigBee 技术,提出将 RFID 和 SIM 集成一卡,使用手机作为统一的小区门禁、停车场等识别卡。选用 PC 作为总控制平台,2440开发板外接RFID 模块作为身份识别,GSM 模块（内含 SIM 卡）作为信息同步、ZigBee 模块作为无线网络节点,在 C2440嵌入式开发平台上,采用 QT4模拟实现实现停车场、楼宇门禁一体化管理。     

用CPLD实现SRAM工艺FPGA的安全应用

提出了一种利用CPLD产生的伪随机码来加密SRAM工艺FPGA的方法,并详细介绍了具体的电路和VHDL代码。     

On Composite Leakage Current Maximization

Sub-threshold, gate and reverse biased junction band-to-band tunneling leakage currents depend on the logic inputs of a CMOS circuit. In this paper, we consider all leakage currents together and generate pattern with the objective of maximizing the overall leakage current to avoid any optimism in leakage current estimation. The computation involves Boolean reasoning on a pre-characterized set of interconnected gates. This problem is known to be computationally intractable. We propose a heuristic with reduced complexity by looking for a lower and an upper bound instead. The bounds tighten progressively with computation and converge asymptotically on a provably exact solution. By appropriately setting the objective function, the same algorithm may also be applied to find the pattern that minimizes the leakage power in the system idle state, which is considered to be ∼50% of the total power consumed in the current technology generations.

图形处理器片段处理单元的设计与实现

针对图形处理器三维引擎中对图形的后期处理需求,实现片段写入帧缓冲区前的测试、混合、逻辑操作、累积、清除和屏蔽等关键功能。分析并提取了OpenGL核心库中的片段处理相关函数,确定了片段处理单元要实现的功能;合理安排多个片段处理功能的执行顺序,设计了基于流水线的片段处理单元结构;采用Verilog HDL对电路进行描述,采用 Cadence NC-Verilog 仿真工具进行虚拟验证,采用 Xilinx 的 ISE 工具进行综合,并在 Xilinx Virtex6 XC6VLX760 FPGA上进行原型验证,电路工作频率可以达到180 MHz,测试功能正确。在SMIC 65 nm CMOS工艺下,采用Synopsys Design-Compiler对设计进行综合,电路工作频率达到300 MHz,满足设计需求。     

超声检测中单通道变多通道信号切换控制

针对小模数齿轮缺陷自动检测的特点,采用逻辑门、总线缓冲器74LS126和固态继电器组合实现单通道变多通道的切换控制,以达到单通道探伤仪当多通道使用的目的。     

一种FPGA抗辐射布线算法设计

随着集成密度的增大以及工作电压的降低,基于SRAM的FPGA芯片更加容易受到单粒子翻转的影响。提出了一种基于通用布局布线工具VPR的抗辐射布线算法,通过改变相关布线资源节点的成本函数,来减少因单粒子翻转引起的桥接错误,并与VPR比较下板测试结果。实验结果表明,该布线算法可以使芯片的容错性能提升20%左右,并且不需要增加额外的硬件资源或引入电路冗余。