可编程增益多通道数据采集系统研究

本文提出了一种利用现场可编程门阵列（FPGA）、仪表运算放大器AD623和高精度AD转换器实现多通道数据数据采集系统的原理.通过对FPGA进行编程配置,可以对不同通道输入的伏值不同的电压信号分别设置增益,使每一个通道输出的信号正好在AD采集所需要的信号范围内,满足了采集要求.实验结果表明该设计结构简单、体积小、适用性强、性能优良、可控性好、能够满足大部分试验和科研过程的需求,具有很广泛的适用性.     

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

模拟电路在线故障检测与诊断的FPGA实现

选择节点电压、幅频特性和相频特性构成故障特征向量集,并根据多通道宽带数据采集接口和驱动程序,给出全数字式的正交幅相特性实时检测方法。利用网络分析与信息融合技术,设计一种模拟电路在线检测和诊断方案,并在现场可编程门阵列硬件系统中进行实现,以解决诸多模拟电路故障诊断算法缺乏测试平台而停留在仿真阶段的问题。实例分析结果表明,该系统可有效识别电路软故障,在存在元件容差的情况下,其识别准确率高达96％,时间消耗低于60ms。     

基于 RFID-SIM 的小区无线门禁系统

针对现代小区各种智能管理系统需要多种智能卡识别给用户带来使用不便、信息不能共享等问题,结合射频识别技术、SIM 技术和 ZigBee 技术,提出将 RFID 和 SIM 集成一卡,使用手机作为统一的小区门禁、停车场等识别卡。选用 PC 作为总控制平台,2440开发板外接RFID 模块作为身份识别,GSM 模块（内含 SIM 卡）作为信息同步、ZigBee 模块作为无线网络节点,在 C2440嵌入式开发平台上,采用 QT4模拟实现实现停车场、楼宇门禁一体化管理。     

基于ARM的逻辑门电路手绘草图识别

针对电路草图识别主要在计算机上完成以及只能识别电路元件的问题,设计一个在ARM处理器和Linux系统上实现的逻辑门电路草图整图识别系统。采取在线识别的方式对触摸屏上输入的手绘笔画进行分段识别、组合、分类得到门电路的图元,按图元顺序建立图元列表,分割出逻辑门图元组合,重构门电路整图。实验证明该系统对逻辑门电路草图有很高的识别率。     

Capacitively coupled transmission line pulsing cc-TLP––a traceable and reproducible stress method in the CDM-domain

This paper describes a new test method called capacitively coupled transmission line pulsing cc-TLP. It is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance. The test results are compared with the ESD thresholds obtained by CDM tests. The cc-TLP results correlate well with the CDM data.     

用户可编程门阵列

第一代的可编程逻辑器件(PLD)以1片器件代替5至10片TTL器件,最新一代可编程器件FPGA可以代替40至400片小规模集成电路。本文介绍四种可编程门阵列的基本结构和主要性能,并给出采用该类器件设计电路的编程技术。     

滑动水口综述

介绍了滑动水口的起源和发展概况,阐述了滑动水口工作原理、水口结构形式及配套机构组成.滑动水口种类很多,分类方式也不同.国内使用的水口系列产品,大多是由国外引进消化而来,也有些是自行设计的.但国内外水口产品还存在着一些区别,直接影响水口国产化进程,这需要做更多的工作,来发展国内水口系列.     

滑模技术在某电站闸门井混凝土施工中的应用

某电站闸门井深达43m,如果采用常规混凝土施工方法,时间长、成本高,难以满足工期要求.经比较选择,该电站闸门井的浇筑采用滑模技术,确保了施工进度,施工质量较好,同时相对常规施工方法大大节约成本。