A novel low-latency DRAM based on the bitline-discharge rate

As well known by computer architects, the performance gap between the processor and the memory has been increasing over the years. This causes what is known as the memory wall. In order to alleviate the problem, a novel fast readout scheme is proposed in this article for the single-transistor single-capacitor dynamic random-access memory (1T-1C DRAM) cells. The proposed scheme works in the current domain in which the difference between the discharging rates of the bitline in the cases of ‘1’ and ‘0’ readings is detected. The proposed scheme is analysed quantitatively and compared with the conventional readout scheme. It is verified by simulation adopting the 45 nm CMOS Berkley predictive-technology model (BPTM) and shows 44 and 7.7% reductions in the average read-access and cycle times, respectively, as compared to the conventional readout scheme. It is also shown that the power is saved according to the proposed scheme if the probability of occurrence of ‘0’ storage exceeds 66.7%. This minimum value can be alleviated, however, at the expense of a smaller saving in the average read-access time. The impacts of process variations and technology scaling are also taken into account.     

光电子显微术的原理和应用

近十年来,光电子显微技术取得了长足进步并已商业化。光电子显微是一种高衬度的成像技术,对材料表面电子结构高度敏感。本文介绍光电子显微镜的成像原理,并着重分析其衬度机制。简要总结光电子显微术在表面结构分析,表面化学,磁学,以及半导体器件表征等方面的应用。目前光电子显微术的两个重要发展方向是利用同步辐射光源和脉冲激光光源做激发源;利用脉冲激光的多光子激发光电子显微术可以对较高功函数（大于光子能量）的材料成像;而脉冲时间分辨光电子显微术可用来研究表面瞬态电子的弛豫动力学机制。文章介绍了在实现飞秒时间分辨以及多光子激发的光电子显微方面的进展。我们利用多光子光电显微术对溅射制备的纳米结构银薄膜表面进行成像,结果表明多光子成像照片上存在一些高强度的亮点,而在单光子成像照片未观察到类似现象。推测这些亮点源于纳米结构银表面的等离子激元的高局域选择性激发。文章还介绍了利用光电子显微术原位观察CuZnAl形状记忆合金的热诱导相变。     

一种适用于低压高速嵌入式应用的2T P沟道纳米晶存储器件

本文基于嵌入式应用的低压、高速要求,提出了一种基于2T结构的P沟道纳米晶存储新型结构。该器件采用带带隧穿激发热电子注入(BTBTIHE)的编程方式,可以同时实现高速、低功耗编程。同时采用2T结构以简化外围高压和读出电路。该器件具有良好的存储特性,包括高编程速度（5us编程脉冲下获得1.1V窗口）和优异的数据保持特性（在10年的保持时间电荷损失仅为20%）。该器件在嵌入式非挥发存储领域具有很强的应用潜力。     

Fast complex memory polynomial-based adaptive digital predistorter

Today's 3G wireless systems require both high linearity and high power amplifier (PA) efficiency. The high peak-to-average ratios of the digital modulation schemes used in 3G wireless systems require that the RF PA maintain high linearity over a large range while maintaining this high efficiency; these two requirements are often at odds with each other with many of the traditional amplifier architectures. In this article, a fast and easy-to-implement adaptive digital predistorter has been presented for Wideband Code Division Multiplexed signals using complex memory polynomial work function. The proposed algorithm has been implemented to test a Motorola LDMOSFET PA. The proposed technique also takes care of the memory effects of the PA, which have been ignored in many proposed techniques in the literature. The results show that the new complex memory polynomial-based adaptive digital predistorter has better linearisation performance than conventional predistortion techniques.     

On Design of Parallel Memory Access Schemes for Video Coding

Some of the modern powerful digital signal processors (DSPs) have byte-addressable internal data memory. This property is valuable especially in computationally demanding inter frame video encoding, where data accesses are typically unaligned according to word boundaries. The byte-addressable memory allows load or store command to start accessing from any byte-address, providing at most as many successive bytes from subsequent addresses as data bus can handle in parallel. Maybe the simplest way to construct such a byte-addressable memory is to use N 8-bit memory modules or banks to be accessed in parallel, when N is data bus width in bytes. However, in addition to byte-addressable subsequent bytes, memory consisting of parallel memory modules can provide much more versatile addressing capabilities with reasonable implementation cost. Versatile access formats can significantly reduce the need for data reordering in the register file. At first, we provide motivation for using parallel memory architecture with versatile access formats as an internal on-chip data memory of modern DSP. After this, notations are described and general view of parallel memory design is given. We propose some example parallel data memory architecture designs with data access formats especially helpful in H.263 encoding and MPEG-4 core profile motion and texture encoding. The examples are given for different data bus widths (16, 32, 64, and 128 bits). Finally, performance is shortly compared to other memory architectures and area, delay, and power figures are estimated.Jarno K. Tanskanen was born in Joensuu, Finland in 1975. He studied analog and digital electronics in the Department of Electrical Engineering, and computer architecture in the Department of Information Technology at Tampere University of Technology, where he received his M.Sc. degree in 1999. He is currently working as a research scientist in the Institute of Digital and Computer Systems at TUT. His Dr.Tech. research concerns parallel processing of video compression. jarno.tanskanen@tut.fiReiner Creutzburg received his Diploma in Mathematics in 1976 and attained his Ph.D. in Mathematics in 1984 from the Rostock University, Germany. Prof. Creutzburg has published 3 books, filed 2 patents, and produced approximately 100 articles, preprint, and conference papers. Professional Experience: Since 2000—Part-time Professor for Multimedia technology, Tampere University of Technology, Finland. Since 1992—Full-time Professor of Computer Science, Fachhochschule Brandenburg-University of Applied Sciences, Brandenburg, Germany. 1990 to 1992—Assistant Professor, University of Karlsruhe, Institute of Algorithms and Cognitive Systems, Germany. 1987 to 1989—Head of the Research Section Image Processing. 1986 to 1989—Founder and Head of the International Base Laboratory of Image Processing and Computer Graphics for East European countries at the Central Institute of Cybernetics and Information Processes of the Academy of Sciences (Berlin), Germany. 1976 to 1989—Researcher and Assistant Professor in various Universities and the Academy of Sciences, Central Institute of Cybernetics and Information, Berlin. creutzburg@fh-brandenburg.deJarkko T. Niittylahti was born in Orivesi, Finland, in 1962. He received the M.Sc, Lic.Tech, and Dr.Tech degrees at Tampere University of Technology (TUT) in 1988, 1992, and 1995, respectively. From 1987 to 1992, he was a researcher at TUT. In 1992–93, he was a researcher at CERN in Geneva, Switzerland. In 1993–95, he was with Nokia Consumer Electronics, Bochum, Germany, and in 1995–97 with Nokia Research Center, Tampere, Finland. In 1997–2000, he was a Professor at Signal Processing Laboratory, TUT, and in 2000–2002 at Institute of Digital and Computer Systems, TUT. Currently, he is a Docent of Digital Techniques at TUT and the managing director of Staselog Ltd. He is also a co-founder and President of Atostek Ltd. He is interested in designing digital systems and architectures. jarkko.niittylahti@tut.fi     

超高温环境下航天器数据记录器防热结构设计

通过用ANSYS软件热仿真数据存储器在1100℃下工作半小时后壳体的温度分布情况,介绍了怎样设计数据记录器的壳体,可使存储器部分有效地回收。并通过有限元分析的直接法,列出了各种材料上所设节点的温度计算矩阵方程,用MATLAB计算出各节点温度结果,再与用ANSYS软件仿真出来的试验结果进行比较,确定试验结果的正确性一一即壳体结构在超高温下工作的可行性。     

基于IAR EW430开发环境的FRAM应用研究

本文基于TI的MSP-EXP430FR5739 LaunchPad硬件评估套件和IAR EW430 IDE开发环境,研究了MSP430FR5739型MCU的FRAM分区配置方法,分别采用程序代码关键字声明法及面对复杂应用满足更高定制要求时修改XLINK配置文件法共两种方法实现了分区调配,编写了相应测试程序进行实验,验证结果达到了预期.同时对实际应用中FRAM分区后应进行MPU保护做出阐述,本文提出的方法可用于MSP430FR系列其他型号MCU器件的FRAM调配.     

菱形NiFe薄膜单元的自发磁化及剩磁状态的研究

利用微磁学方法系统研究了纳米尺度的NiFe薄膜菱形单元的自发磁化状态及剩磁状态。研究结果表明,在不同的尺寸下,菱形单元将有不同的自发磁化状态及剩磁状态。在单元的长宽尺寸小于某个临界尺寸时,菱形单元结构呈现单畴态。同时还分析了菱形NiFe单元作为磁性随机存储器(MRAM)存储单元时的要求。     

基于小波的汇率波动序列长记忆性研究

提出了基于小波方差的时间序列长记忆性分析方法，用该方法对汇率波动序列进行了分析，得到了长记忆参数的精确值。引入了关联尺度函数，对各汇率波动序列长记忆效应的大小程度进行了验证。结果表明各汇率波动序列存在长记忆效应，并且长记忆参数d值越大，汇率波动序列所受历史信息的影响就越强。     

Reconfigurable and Latchable Shape‐Morphing Dielectric Elastomers Based on Local Stiffness Modulation

Programmable soft materials exhibiting dynamically reconfigurable, reversible, fast, and latchable shape transformation are key for applications ranging from wearable tactile actuators to deployable soft robots. Multimorph soft actuator sheets with high load‐bearing capacity are reported, capable of bending on multiple axis, made by combining a single dielectric elastomer actuator (DEA) with two layers of shape memory polymers (SMPs) fibers and an array of stretchable heaters. The rigidity of the SMP fibers can be reduced by two orders of magnitude by Joule heating, thus allowing the orientation and location of soft and hard regions to be dynamically defined by addressing the heaters. When the DEA is then actuated, it bends preferentially along the soft axis, enabling the device to morph into multiple distinct configurations. Cooling down the SMPs locks these shape changes into place. A tip deflection angle of over 300° at 5 kV is achieved with a blocking force of over 27 mN. Devices using two antagonistic DEAs are also reported that attain more complex shapes. Multimorphing is demonstrated by gripping objects with different shapes. An analytical model is developed to determine the design parameters that offers the best trade‐off between large actuation and high holding forces.