Profiling Voids Embedded in a Slab by a Non-Linear Model

In this paper, by applying a non linear model for the electromagnetic inverse scattering, a technique for the dielectric profiling of a planarly layered medium is investigated and applied to void localization and diagnostics inside a homogeneous lossless slab (one-dimensional geometry). Data are collected under plane wave multifrequency normal incidence. Suitable finite dimensional representations for the unknown functions are introduced and their influence on the model is discussed. The resulting functional equation is solved by the method of weighted residuals and the solution algorithm amounts to minimizing a non quadratic function, where particular attention is devoted to reduce the occurrence of local minima. Finally, the inversion algorithm is validated by applications to both simulated and experimental data.     

Growth of large-diameter ZnTe single crystals by liquid-encapsulated melt growth methods

The 80-mm-diameter ZnTe single crystals were successfully obtained by the liquid-encapsulated Kyropoulos (LEK) method. Both 〈100〉- and 〈110〉-oriented single crystals were reproducibly grown by using ZnTe seed crystals. Furthermore, 80-mm-diameter, 〈100〉 and 〈110〉 ZnTe single crystals were obtained by the pulling method. The etch pit densities (EPDs) of the grown crystals by the LEK and pulling methods were lower than 10,000 cm⁻². The strain in the grown crystals by the pulling method was lower than that of LEK crystals.     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

电子元器件可靠性增长的分析技术

从元器件可靠性物理分析技术角度,系统地阐述了失效信息的收集与分析、失效分析、破坏性物理分析、密封器件内部气氛分析、失效模式及机理与工艺的相关性分析、失效模式与影响分析等元器件的质量与可靠性分析技术。将元器件质量与可靠性分析技术融入元器件产品设计、制造过程是实现元器件可靠性增长的必然趋势。     

布里奇曼法生长碲镉汞晶体的缺陷及其展望

简单介绍了布里奇曼法生长碲镉汞晶体的主要缺陷以及缺陷的控制原理，回顾了国内进行磅镉汞晶体生长的布里奇曼法及加速坩埚旋转技术的布里奇曼法（ＡＣＲＴ－Ｂ）研究的情况，并提出了进一步研究的问题。     

Lateral epitaxial overgrowth of GaN films on SiO2 areas via metalorganic vapor phase epitaxy

Lateral epitaxial growth and coalescence of GaN regions over SiO₂ masks previously deposited on GaN/AlN/6H-SiC(0001) substrates and containing 3 μm wide rectangular windows spaced 7 μm apart have been achieved. The extent and microstructural characteristics of these regions of lateral overgrowth were a complex function of stripe orientation, growth temperature, and triethylgallium (TEG) flow rate. The most successful growths were obtained from stripes oriented along 〈1 00〉 at 1100°C and a TEG flow rate of 26 μmol/min. A density of ∼10⁹ cm⁻² threading dislocations, originating from the underlying GaN/AlN interface, were contained in the GaN grown in the window regions. The overgrowth regions, by contrast, contained a very low density of dislocations. The surfaces of the coalesced layers had a terrace structure and an average root mean square roughness of 0.26 nm.     

Amorphous chromium silicide formation in hydrogenated amorphous silicon

The interaction between thin films of hydrogenated amorphous silicon and sputter-deposited chromium has been studied. Following deposition of the chromium films at room temperature, the films were annealed over a range of times and temperatures below 350°C. It was found that an amorphous silicide was formed only a few nanometers thick with the square of thickness proportional to the annealing time. The activation energy for the process was 0.55±0.05 eV. The formation process of the silicide was very reproducible with the value of density derived from the thickness and Cr surface density being close to the value for crystalline CrSi₂ for all films formed at temperatures ≤300°C. The specific resistivity of the amorphous CrSi₂ was ≈600 μΩ·cm and independent of annealing temperature.     

Compositional, structural, optical and electrical characterization of CulnTe2 grown by the tellurization of stoichiometric Cu and in in the liquid phase

A new method to grow single crystals with stoichiometry close to 1:1:2 of CuInTe₂, an important member of the Cu-III-VI₂ family of semiconductors is described. This consists of tellurization in the liquid phase of stoichiometric Cu and In and later solidification under directional freezing. It is found from energy dispersive spectroscopy that the ingots obtained with the evaporation temperature (T_t) of Te at 590 and 635°C were very close to the ideal stoichiometry 1:1:2. Samples of all ingots obtained with T_t between 530 and 690°C, as studied by x-ray and differential thermal analysis, were of single phase having chalcopyrite structure and p-type conductivity. Optical and electrical characterization of different ingots were made. The acceptor ionization energy E_A and the density of states effective mass m _p ^* of the holes are estimated from the temperature dependence of the hole concentration p in samples of different ingots. m _p ^* = (0.78 ± 0.02) m_e agrees quite well with the reported value. From a combined analysis of the variation of E_A with p^1/3 and the knowledge of molecularity and valence stoichiometry of each sample, it is established that the shallow acceptor level observed in different samples with E_A (0) ⋍ 30 meV is due to V_In.     

Growth and characterization of GaSb bulk crystals with low acceptor concentration

GaSb bulk single crystals with low acceptor concentration were grown from a bismuth solution by the traveling heater method. The result is isoelectronic doping by Bi which gives a variation of the opto-electronic properties as a function of grown length as well as a pronounced microscopic segregation. Photoluminescence spectra at 4K show a decrease of the natural acceptor during growth, which is confirmed by Hall measurements. The electrical properties of this isoelectronic doped GaSb are hole concentrations and mobilities of N_A − N_D = 1.7 × 10¹⁶ cm⁻³ and μ = 870 cm²Vs at room temperature and N_A-N_D = 1 × 10¹⁶ cm⁻³ and μ = 4900 cm²/Vs at 77K, respectively. The lowest p-type carrier concentration measured at 300K is N_A − N_D = 3.3 × 10¹⁵ cm⁻³     

Multicomponent zone melting growth of ternary InGaAs bulk crystal

In_xGa_1-x As crystals with x = 0.25-0.08 have been successfully grown on GaAs seeds by a method of multicomponent zone melting growth. Its alloy composition is found to be controlled by the growth temperature. Within an ingot, a good uniformity in the alloy composition along the direction normal to the growth is also achieved. The alloy composition gradually changes along the growth direction in the ingot, and this change is well explained by a temperature profile in the growth furnace.