可编程光学二值双轨逻辑门

基于双轨逻辑,本文提出一种可级联的并行二值逻辑门。所有十六种二值逻辑运算可以采用偏振半波相延编程来实现。也提出了用电光晶体实现实时编程的方法。本文中给出了实验结果。     

单层工业厂房可靠性的模糊综合评判

主要研究了单层工业厂房可靠性模糊综合评判法的基本理论与实施方法．通过一工程实例，表明用这种定量方法来处理厂房可靠性评判中的大量不确定信息是科学、合理而又实用的．     

Resolution calculus for the first order linear logic

This paper presents a formulation and completeness proof of the resolution-type calculi for the first order fragment of Girard's linear logic by a general method which provides the general scheme of transforming a cutfree Gentzen-type system into a resolution type system, preserving the structure of derivations. This is a direct extension of the method introduced by Maslov for classical predicate logic. Ideas of the author and Zamov are used to avoid skolomization. Completeness of strategies is first established for the Gentzen-type system, and then transferred to resolution. The propositional resolution system was implemented by T. Tammet.     

基于参考点的模糊知识表示

本文分析了模糊关系模型的知识表示途径，并由此提出基于参考点的模糊知识表示，分析了它与人类记忆经验性知识的相信性，并证明模糊关系模型能以任意精度逼近具有有限个极值点的有界连续函数。     

Safety,liveness and fairness in temporal logic

In this paper we present syntactic characterization of temporal formulas that express various properties of interest in the verification of concurrent programs. Such a characterization helps us in choosing the right techniques for proving correctness with respect to these properties. The properties that we consider include safety properties, liveness properties and fairness properties. We also present algorithms for checking if a given temporal formula expresses any of these properties.This work is partly supported by NSF grant CCR-9212183. A preliminary version of this paper appeared in the Fourth ACM Symposium on Principles of Distributed Computing.     

A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol

We present a formal model of asynchronous communication between two digital hardware devices. The model takes the form of a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into that consumed by an independently clocked processor, given the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on communications at ISO protocol level 1 (physical level). We use the model to show that an 18-bit/cell biphase mark protocol reliably sends messages of arbitrary length between two processors provided the ratio of the clock rates is within 5% of unity.     

New and used temporal models: An issue of time

TheSpecial Issue on Applications of Temporal Models raises many issues of time: What are the important properties of time? How can time be best represented? How can one reason about time-dependent properties? What are the important directions of temporal research? This introductory piece very briefly surveys the current wide variety of temporal models, temporal reasoning methods, and applications to time-varying phenomena. Promising areas of investigation such as the verification of concurrent systems, knowledge-base representation methods, and dealing with theFrame Problem pass in fleeting review. Brief introductions to each of the works in the volume close the section.     

A fuzzy diagnosis approach using dynamic fault trees

By incorporating digraph models, fault trees and fuzzy inference mechanisms in a unified framework, a novel approach for fault diagnosis is developed in this work. To relieve the on-line computation load, the fault origins considered in diagnosis are limited to the basic events in the cut sets of a given fault tree. The symptom occurrence order associated with each root cause is derived from system digraph with the qualitative simulation techniques. The implied candidate patterns are enumerated according to two proposed theorems and then encoded in the inference system with IF-THEN rules. The simulation results show that the proposed approach is not only feasible but also capable of identifying the most likely cause(s) of a hazardous event at the earliest possible time.     

异步时序型PAL解析方法的研究及解析结果分析

本文就异步时序现ＰＡＬ的解析，提出了一种状态图遍历算法。     

Workload Distribution in Fault Simulation

Simulation at the gate level is computationally very expensive.Parallel processing is one technique to reduce simulation time.Possessing knowledge of the distribution of computational activity insimulation can aid in parallelizing it efficiently. We present a newcharacterization of the distribution of the computational workload infault simulation. An empirical analysis shows that the workloaddistribution is circuit specific, and is largely independent of thevector set being simulated. An inexpensive method to predict theworkload distribution is also discussed.