V-型皱褶芯材承压的均质化等效模型

采用代理模型获得V-型皱褶芯材等效屈服应力、等效平台应力和几何参数之间的关系,并据此提出了一种承受静力/准静力面外压缩的V-型皱褶芯材均质化等效模型。计算结果与试验结果的对比表明:皱褶芯材的均质化等效模型可以很好地模拟原结构的弹塑性力学特性,并能大大减少计算耗时。对于皱褶夹芯板在结构中,特别是抗坠毁吸能结构中的应用,本文的等效模型提供了一种高效率的计算及优化手段。     

Memory Fault Modeling Trends: A Case Study

In recent years, embedded memories are the fastest growing segment of system on chip. They therefore have a major impact on the overall Defect per Million (DPM). Further, the shrinking technologies and processes introduce new defects that cause previously unknown faults; such faults have to be understood and modeled in order to design appropriate test techniques that can reduce the DPM level. This paper discusses a new memory fault class, namely dynamic faults, based on industrial test results; it defines the concept of dynamic faults based on the fault primitive concept. It further shows the importance of dynamic faults for the new memory technologies and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and sets a direction for further research.     

Special issue on system-integrated intelligence. New challenges for product and production engineering

The ubiquitous development of information and communication technology enables new opportunities for products as well as for production and manufacturing systems. These systems will be able to learn and adapt their behaviour during the systems operation for a continuos optimization. This results in an increasing structural complexity and dynamics of products, production networks, processes and organizations, which in turn requires an on-going adaption and reinvention of the organizing principles and solutions. Therefore, new products as well as their corresponding production and logistic processes spawn research activities in the field of advanced information techniques and system integrated intelligence to cope with the complexity and dynamics of future manufacturing networks.     

Design and Realization of CPW Circuits Using EC-ANN Models for CPW Discontinuities

将一种精确高效的等效电路训练人工神经网络模型引入共面波导不连续性结构建模.该建模算法继承了等效电路模型和电磁仿真人工神经网络模型的优点.此次开发并得到验证的共面波导不连续性结构模型包括:台阶段、叉指电容、对称十字节和螺旋电感.这些模型嵌入CAD仿真工具可以完成电路的设计、仿真和优化,最后通过一个GaAs工艺的共面波导带通滤波器的设计与实现验证了模型的有效性.     

Toward Robust Speech Recognition and Understanding

The principal cause of speech recognition errors is a mismatch between trained acoustic/language models and input speech due to the limited amount of training data in comparison with the vast variation of speech. It is crucial to establish methods that are robust against voice variation due to individuality, the physical and psychological condition of the speaker, telephone sets, microphones, network characteristics, additive background noise, speaking styles, and other aspects. This paper overviews robust architecture and modeling techniques for speech recognition and understanding. The topics include acoustic and language modeling for spontaneous speech recognition, unsupervised adaptation of acoustic and language models, robust architecture for spoken dialogue systems, multi-modal speech recognition, and speech summarization. This paper also discusses the most important research problems to be solved in order to achieve ultimate robust speech recognition and understanding systems. Dr. Sadaoki Furui is currently a Professor at Tokyo Institute of Technology, Department of Computer Science. He is engaged in a wide range of research on speech analysis, speech recognition, speaker recognition, speech synthesis, and multimodal human-computer interaction and has authored or coauthored over 450 published articles. From 1978 to 1979, he served on the staff of the Acoustics Research Department of Bell Laboratories, Murray Hill, New Jersey, as a visiting researcher working on speaker verification. He is a Fellow of the IEEE, the Acoustical Society of America and the Institute of Electronics, Information and Communication Engineers of Japan (IEICE). He was President of the Acoustical Society of Japan (ASJ) from 2001 to 2003 and the Permanent Council for International Conferences on Spoken Language Processing (PC-ICSLP) from 2000 to 2004. He is currently President of the International Speech Communication Association (ISCA). He was a Board of Governor of the IEEE Signal Processing Society from 2001 to 2003. He has served on the IEEE Technical Committees on Speech and MMSP and on numerous IEEE conference organizing committees. He has served as Editor-in-Chief of both Journal of Speech Communication and the Transaction of the IEICE. He is an Editorial Board member of Speech Communication, the Journal of Computer Speech and Language, and the Journal of Digital Signal Processing. He has received the Yonezawa Prize and the Paper Awards from the IEICE (1975, 88, 93, 2003), and the Sato Paper Award from the ASJ (1985, 87). He has received the Senior Award from the IEEE ASSP Society (1989) and the Achievement Award from the Minister of Science and Technology, Japan (1989). He has received the Technical Achievement Award and the Book Award from the IEICE (2003, 1990). He has also received the Mira Paul Memorial Award from the AFECT, India (2001). In 1993 he served as an IEEE SPS Distinguished Lecturer. He is the author of “Digital Speech Processing, Synthesis, and Recognition” (Marcel Dekker, 1989, revised, 2000) in English, “Digital Speech Processing” (Tokai University Press, 1985) in Japanese, “Acoustics and Speech Processing” (Kindai-Kagaku-Sha, 1992) in Japanese, and “Speech Information Processing” (Morikita, 1998) in Japanese. He edited “Advances in Speech Signal Processing” (Marcel Dekker, 1992) jointly with Dr. M.M. Sondhi. He has translated into Japanese “Fundamentals of Speech Recognition,” authored by Drs. L.R. Rabiner and B.-H. Juang (NTT Advanced Technology, 1995) and “Vector Quantization and Signal Compression,” authored by Drs. A. Gersho and R. M. Gray (Corona-sha, 1998).     

基于高斯混合模型的车辆字符识别算法

在基于统计方法的车牌字符识别算法中,为了更有效地描述车牌字符特征的类条件概率密度,提出了一种基于高斯混合模型(GMM)的识别方法.首先采用Gabor变换来提取车牌字符的特征参数,然后通过GMM来逼近字符特征的类条件概率密度分布,最后根据得到的类条件概率密度分布函数构造贝叶斯分类器.其中,GMM的参数估计采用EM算法.实验表明,这种方法具有良好的字符识别效果、较强的鲁棒性以及较大的应用价值.     

有色噪声的扩散过程模型

研究使用基于随机微分方程的扩散过程模型产生有色噪声.首先给出Markov扩散过程的平稳分布,该分布给出了扩散过程模型中的漂移系数、扩散系数和有色噪声概率密度分布之间的关系;选择扩散过程模型中的扩散系数为x的一次幂,其系数决定了所生成噪声的相关特性;数值算法使用Milstein高阶法.以三元独立积构造的G-分布雷达杂波为例进行仿真分析,验证所提出方法的准确性和有效性.     

A low light natural image statistical model for joint contrast enhancement and denoising

We study the problem of joint low light image contrast enhancement and denoising using a statistical approach. The low light natural image in the band pass domain is modeled by statistically relating a Gaussian scale mixture model for the pristine image, to the low light image, through a detail loss coefficient and Gaussian noise. The detail loss coefficient is statistically described using a posterior distribution with respect to its estimate based on a prior contrast enhancement algorithm. We then design our low light enhancement and denoising (LLEAD) method by computing the minimum mean squared error estimate of the pristine image band pass coefficients. We create the Indian Institute of Science low light image dataset of well-lit and low light image pairs to learn the model parameters and evaluate our enhancement method. We show through extensive experiments on multiple datasets that our method helps better enhance the contrast while simultaneously controlling the noise when compared to other state of the art joint contrast enhancement and denoising methods.     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

可靠性预计模型的参数敏感度分析

利用蒙特卡罗仿真 ,对可靠性预计模型中的主要参数例如温度、电应力、元器件构成比例、环境系数、质量系数等等 ,对设备可靠性预计值的影响程度进行了分析 ;比较了不同手册的参数预计参数敏感度 ;对可靠性设计中应注意的问题提出了建议。