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This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock. 相似文献
233.
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing 总被引:2,自引:0,他引:2
As System on a Chip (SoC) testing faces new challenges, some new test architectures must be developed. This paper describes a Test Access Mechanism (TAM) named CAS-BUS that solves some of the new problems the test industry has to deal with. This TAM is scalable, flexible and dynamically reconfigurable. The CAS-BUS architecture is compatible with the IEEE P1500 standard proposal in its current state of development, and is controlled by Boundary Scan features.This basic CAS-BUS architecture has been extended with two independent variants. The first extension has been designed in order to manage SoC made up with both wrapped cores and non wrapped cores with Boundray Scan features. The second deals with a test pin expansion method in order to solve the I/O bandwidth problem. The proposed solution is based on a new compression/decompression mechanism which provides significant results in case of non correlated test patterns processing. This solution avoids TAM performance degradation.These test architectures are based on the CAS-BUS TAM and allow trade-offs to optimize both test time and area overhead. A tool-box environment is provided, in order to automatically generate the needed component to build the chosen SoC test architecture. 相似文献
234.
舰船水声隐身技术(二) 总被引:2,自引:0,他引:2
本文探讨了水声隐身性能对舰船战技术性能的影响 ,舰船水噪声的主要噪声源、水噪声的治理措施及其展望。 相似文献
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纳米TiO2 是一种宽禁带半导体光催化剂 ,可用于污水处理、空气净化、灭菌消毒、医疗、化学合成、贵金属提取冶金、能源材料等多个领域 ,未来的研究发展重点应是实用化纳米TiO2 光催化剂的开发及高效光反应器的研制。 相似文献
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Ryba Nancy L.; Cooper Virginia G.; Zapf Patricia A. 《Canadian Metallurgical Quarterly》2003,34(5):499
What is the current standard of practice for evaluations of juvenile competence to stand trial (JCST)? The present study surveyed psychologists regarding the practices used when conducting JCST evaluations. Respondents rated the importance of 17 elements that might be included in a JCST evaluation report. Of these elements, 7 were considered essential by 70% or more of respondents, with 9 additional elements rated as either essential or recommended. A majority of respondents felt that the use of psychological and forensic instruments was important. A list of tests used is provided, and the implications for the development of standards and policy are discussed to provide practitioners with additional knowledge that will help to further the state of the discipline. (PsycINFO Database Record (c) 2010 APA, all rights reserved) 相似文献
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总结了小浪底水利枢纽投运初期的水沙情况、孔板洞原型观测试验、调水调沙试验和枢纽的安全监测情况,介绍了大坝防渗、转轮裂纹问题的处理方案,总结了枢纽在防洪、防凌、减淤、供水和发电等方面发挥的作用。试验和对监测资料的分析表明,枢纽运行稳定,孔板洞设计合理、消能效果显著,各部位建筑物性态稳定,发挥了巨大的综合效益。 相似文献