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91.
92.
SAR图像固有的斑点噪声严重影响了图像的判读和后续处理,因此抑制SAR图像斑点噪声显得尤其重要。一个良好的斑点噪声抑制算法应该在降低斑点噪声的同时,能很好地保持图像的细节特征,但现有的去噪算法没有一种能够完美地解决这个问题的。本文基于SAR图像斑点噪声滤波的重要性以及存在的问题,将整体变分偏微分方程用于去除斑点噪声。根据整体偏微分方程建立了去噪模型,并分析了模型的性能和参数选择的重要性。通过实验验证了该算法的有效性,并以峰值信噪比(PSNR)为评价准则,利用多项式拟合方法选择了最优参数。引入边缘保持指数(EPI),与其他滤波算法比较,本算法在去除噪声的同时较好地保持了边缘。 相似文献
93.
Chang Liu Takao Tsuji Tsutomu Oyama 《IEEJ Transactions on Electrical and Electronic Engineering》2012,7(5):471-477
In the future, a large number of distributed generators are expected to be connected to the distribution system. However, with the connected capacity of distributed generation (DG) increasing, the problems of short‐circuit capacity (SCC) over the interrupting capacity of the circuit breaker (CB) and power loss increases due to reverse power flow from DG are inevitable. In this paper, a reconfiguration methodology based on an optimal algorithm is applied to the distribution system with DG to minimize power loss, taking into account the SCC. Moreover, in order to further reduce the loss, the daily load variation is also considered and the optimal model decided by calculations. Finally, to illustrate its application, the methodology is applied to a case study of a 33‐bus system with decentralized DG units. The results show that this method is obviously able to reduce power loss and make the network operate in the optimal mode with normal load variation, at the same time decreasing the SCC within the interrupting maximum of the faulty CB. Moreover, the whole voltage profile is also improved. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc. 相似文献
94.
J. V. Vosper 《International Journal of Electronics》2013,100(7):759-772
Two groups of three active-RC oscillators that use a single voltage feedback op amp (VFOA) are compared. Linear analysis using a first-order VFOA model shows that all six oscillators have the same maximum oscillation frequency (OF) of 16.67% of the op amp gain-bandwidth product (GBP), despite the fact that based on an ideal VFOA the gain required in the oscillator amplifier section is 3 for one group and 1.5 for the other.Sensitivity of OF to op amp GBP is found to be the same for both groups. Simulation results using a nonlinear VFOA macromodel give good agreement with linear analysis. 相似文献
95.
In recent years, hyperspectral image super-resolution has attracted the attention of many researchers and has become a hot topic in the field of computer vision. However, it is difficult to obtain high-resolution images due to imaging hardware devices. At present, many existing hyperspectral image super-resolution methods have not achieved good results. In this paper, we propose a hyperspectral image super-resolution method combining with deep residual convolutional neural network (DRCNN) and spectral unmixing. Firstly, the spatial resolution of the image is enhanced by learning a priori knowledge of natural images. The DRCNN reconstructs high spatial resolution hyperspectral images by concatenating multiple residual blocks, each containing two convolutional layers. Secondly, the spectral features of low-resolution and high-resolution hyperspectral images are linked by spectral unmixing. This approach aims to obtain the endmember matrix and the abundance matrix. The final reconstruction result is obtained by multiplying the endmember matrix and the abundance matrix. In addition, in order to improve the visual effect of the reconstructed image, the total variation regularity is used to impose constraints on the abundance matrix to enhance the relationship between the pixels. The experimental results of remote sensing data based on ground facts show that the proposed method has good performance and preserves spatial information and spectral information without the need for auxiliary images. 相似文献
96.
97.
一个用于高速信号传输的对PVT变化不敏感的低功耗锁相环 总被引:2,自引:0,他引:2
介绍了一个用于高速信号传输的低功耗锁相环. 提出了一种新的开环校准方法. 该校准通过上电时候进行的开环数字校准很大程度上减轻了工艺变化对电路的影响,相比以前的闭环校准方法,该方法可以显著缩短校准时间. 在这个锁相环中采用了双环路的结构来获得对工艺、温度和环境变化不敏感的环路参数:例如衰减因子、相位裕度等. 还设计了一种新的鉴频鉴相器,它内嵌了电平转换的功能,简化了电路. 该PLL的设计通过小心的供电网络划分来降低电源噪声的耦合. 设计的锁相环路在输出为1.6GHz的时候均方根抖动为3.1ps,而仅消耗约为1mA的电流. 相似文献
98.
This paper proposes a fast-settling frequency-presetting PLL frequency synthesizer. A mixedsignal VCO and a digital processor are developed to accurately preset the frequency of VCO and greatly reduce the settling time. An auxiliary tuning loop is introduced in order to reduce reference spur caused by leakage current. The digital processor can automatically compensate presetting frequency variation with process and temperature, and control the operation of the auxiliary tuning loop. A 1.2 GHz integer-N synthesizer with 1 MHz reference input was implemented in a 0.18 μm process. The measured results demonstrate that the typical settling time of the synthesizer is less than 3 μs, and the phase noise is –108 dBc/Hz@1MHz. The reference spur is –52 dBc. 相似文献
99.
结构可靠性的估计问题是机械可靠性的主要问题之一.强度和应力均为正态变量的结构模式是一种较常见的模式.研究这一模式结构可靠性的区间估计问题.提出了用正态分布变差系数的区间估计结果来处理此模式结构可靠性的区间估计的新方法,给出了正态强度和正态应力的分布参数均未知时,结构可靠性的具有简单表达式的经典精确置信下限,它是此模式结... 相似文献
100.
Soft-edge flip-flop (SEFF) based pipelines can improve the performance and energy efficiency of circuits operating in the super-threshold (supply voltage) regime by enabling the opportunistic time borrowing. The application of this technique to the near-threshold regime of operation, however, faces a significant challenge due to large circuit parameter variations that result from manufacturing process imperfections. In particular, delay lines in SEFFs have to be over-designed to provide larger transparency windows to overcome the variation in path delays, which causes them to consume more power. To address this issue, this paper presents a novel way of designing delay lines in SEFFs to have a large enough transparency window size and low power consumption. Two types of linear pipeline design problems using the SEFFs are formulated and solved: (1) designing energy-delay optimal pipelines for the general usage that requires SEFFs to operate in both the near-threshold and super-threshold regimes, and (2) designing minimum energy consumed pipelines for particular use case with a minimum operating frequency constraint. Design methods are presented to derive requisite pipeline design parameters (i.e., depth and sizing of delay lines in SEFFs) and operating conditions (i.e., supply voltage and operating frequency of the design) in presence of process-induced variations. HSPICE simulation results using ISCAS benchmarks demonstrate the efficacy of the presented design methods. 相似文献