Parallel path consistency

Filtering algorithms are well accepted as a means of speeding up the solution of the consistent labeling problem (CLP). Despite the fact that path consistency does a better job of filtering than arc consistency, AC is still the preferred technique because it has a much lower time complexity. We are implementing parallel path consistency algorithms on multiprocessors and comparing their performance to the best sequential and parallel arc consistency algorithms.^(1,2) (See also work by Kerethoet al. ⁽³⁾ and Kasif⁽⁴⁾) Preliminary work has shown linear performance increases for parallelized path consistency and also shown that in many cases performance is significantly better than the theoretical worst case. These two results lead us to believe that parallel path consistency may be a superior filtering technique. Finally, we have implemented path consistency as an outer product computation and have obtained good results (e.g., linear speedup on a 64K-node Connection Machine 2).     

A VLSI architecture for a half-edge-based corner detector

Corner detection is a low-level feature detection operator that is of great use in image processing applications, for example, optical flow and structure from motion by image correspondence. The detection of corners is a computationally intensive operation. Past implementations of corner detection techniques have been restricted to software. In this paper we propose an efficient very large-scale integration (VLSI) architecture for detection of corners in images. The corner detection technique is based on the half-edge concept and the first directional derivative of Gaussian. Apart from the location of the corner points, the algorithm also computes the corner orientation and the corner angle and outputs the edge map of the image. The symmetrical properties of the masks are utilized to reduce the number of convolutions effectively, from eight to two. Therefore, the number of multiplications required per pixel is reduced from 1800 to 392. Thus, the proposed architecture yields a speed-up factor of 4.6 over conventional convolution architectures. The architecture uses the principles of pipelining and parallelism and can be implemented in VLSI.     

二滩水电站油、水、风系统设备运行与改造

水电站辅助设备的运行直接影响水电站运行的安全性和可靠性。二滩水电站投运初期，油、水、风系统先后出现了许多问题，通过应用新产品和新技术对其进行了改造。为水电厂辅助设备的设计、选型、安装提供了宝贵的经验，并对水电厂辅助设备的检修、调试和运行维护有一定的指导作用。     

Topology preservation of template-based 6-subiteration reduction operations

Generally, a reduction operation (e.g., thinning and shrinking) on 3D binary images can be represented as a set of reduction templates where every object voxel of the image satisfying any template is turned to a background voxel. Generally, it is rather difficult, error-prone and time-consuming for verifying the topological soundness of a 3D parallel reduction operation. This paper proposes sufficient conditions of time complexity O(n) for verifying the topological soundness of 3D parallel 6-subiteration reduction operations of n templates where such a kind of 3D reduction operations is performed alternatively from the six orthogonal directions to turn object voxels to background voxels. By such sufficient conditions, the topology soundness of a 3D 6-subiteration parallel reduction operation can be verified by checking each and every of its templates.     

圆盘锯机性能提升途径

圆盘锯机在线材厂投入使用时不能满足生产的需要：锯切周期太长，锯片使用性能差，经过对设备进行技术改造和对设备操作规程进行优化，以及在操作上加强管理，使之关键指标大幅度提升，为圆盘锯机的使用改善提供了新的思路。     

氧气合理利用决策支持系统和空分装置操作仿真系统

分析了钢铁企业空分系统能源管理的特点 ,并开发出降低空分能耗的应用软件 :氧气合理利用决策支持系统和空分装置操作仿真系统。前者可为决策者提供全面的辅助决策信息和决策支持以降低氧气放散 ,实现氧气的合理利用 ;后者既可实现空分装置运行操作的仿真 ,也可实现空分装置的仿真实验和仿真操作 ,为实施空分装置的节能优化运行提供技术支持     

计算机高速并行通信的实现方案

利用CPLD芯片实现单片机与ISA总线接口之间的高速并行通信，给出系统的总体设计方法及程序框图。采用这种通信方式，在12MHz晶振的MCS51单片机控制的数据采集系统中，可以满足与PCI04 ISA总线接口实时通信的要求，通信速率达200khit／s。在开发工具MAX plusⅡ下，完成了整个设计的输入、编译和仿真，达到了预期效果。本设计方案能够推广应用到计算机的高速并行通信中。     

多码CDMA系统中联合并行干扰抵消与迭代信道估计方法

本文针对多码CDMA系统提出了一种联合并行干扰抵消与迭代信道估计方法。该方法首先通过导频符号对信道进行估计，然后使用RAKE接收机后的软信息对信道参数进行修正，最后通过并行干扰抵消(PIC)去除多码干扰(MCI)。仿真结果表明，经过多次迭代后，该方法可显著地降低多码CDMA系统的误比特率平台。本文同时还给出了信道估计质量、码道数和PIC次数对多码CDMA系统性能的影响。     

Mesh结构P/G布线网络层次化快速分析方法

本文提出了一个基于网络划分的P／G布线网络层次化快速分析方法。其中，对于子网运算，通过对Cholesky分解法三角化对称正定阵的图模型分析，并基于Mesh结构网络的自身特点，提出了一个基于图顶点排序的加速子网分析运算策略；并用基于MPI的并行结构实现了P／G布线网络分析的并行运算。