Method to remove wafer surface particles

A big yield drop has been observed during the automatic inspection (AOI) after the saw stage. A step by step AOI inspection check and defect review is made to see which step made a big yield drop and which kind of defect contributed most to the yield drop. Scanning electron microscope (SEM) and energy dispersive spectrometer (EDS) analysis showed the shape and chemical element of the particle. From the EDS result, particles can be separated into two categories. One was the inorganic related materials, mainly including silicon (Si) element, which came from the saw stage. A design of experiment (DOE) is used to find some reasonable saw relative parameter and optimize it in order to remove the particle from the saw stage. But the quantity of this kind of particle was small. Yield was only improved by less than 5%. Our main effort was to remove another kind of particle which was organic related materials, mainly including carbon (C) and oxygen (O) element. This kind of particle was from tape residue. In order to remove the tape residual, one step was added before the saw stage. Almost all of the tape residual was removed. Finally, the final yield was improved by more than 15%.     

Fault diagnosis in reconfigurable VLSI and WSI processor arrays

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The divide and conquer technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(V^1/2) for the processor arrays considered in this paper, where V is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.     

IC缺陷轮廓的分形插值模型

现用于集成电路(IC)成品率预报及故障分析的缺陷模型均是用圆或正方形来代替真实缺陷的复杂轮廓进行近似建模的,从而在模型中引入了很大的误差。本文利用分形插值的思想直接对真实缺陷的轮廓进行模拟,从而提出了一种新的缺陷轮廓表征模型。实验结果表明：与传统的最大圆模型、最小圆模型及椭圆模型相比,新模型的建模精度有了很大的提高。     

Accurate Whole-Chip Diagnostic Strategy for Scan Designs with Multiple Faults

Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of these block-level techniques are needed in order to successfully diagnose a large chip with multiple faults. In this paper, we present such a strategy. Our strategy is effective in identifying more than one fault accurately. It proceeds in two phases. In the first phase we concentrate on the identification of the so-called structurally independent faults based on a concept referred to as word-level prime candidate, while in the second phase we further trace the locations of the more elusive structural dependent faults. Experimental results show that this strategy is able to find 3 to 4 faults within 10 signal inspections for three real-life designs randomly injected with 5 node-type or stuck-at faults. Part of this work has ever appeared in the proceedings of Asian Test Symposium in 2003. Yu-Chiun Lin received his BS degrees in Electrical Engineering from National Central University in 2000, and MS degree from Electrical Engineering of National Tsing Hua University in 2002. Since then, he has been with Ali Corporation as a design engineer. His current interests include the design of USB controllers and imaging periperals. Shi-Yu Huang received his BS, MS degrees in Electrical Engineering from National Taiwan University in 1988, 1992 and Ph.D. degree in Electrical and Computer Engineering from the University of California, Santa Barbara in 1997, respectively. From 1997 to 1998 he was a software engineer at National Semiconductor Corp., Santa Clara, investigating the System-On-Chip design methodology. From 1998 to 1999, he was with Worldwide Semiconductor Manufacturing Corp., designing the high-speed Built-In Self-Test circuits for memories. He joined the faculty of National Tsing-Hua University, Taiwan, in 1999, where he is currently an Associate Professor. Dr. Huang’s research interests include CMOS image sensor design, low-power memory design, power estimation, and fault diagnosis methodologies.     

Photon-assisted capacitance–voltage study of organic metal–insulator–semiconductor capacitors

The results are reported of a detailed investigation into the photoinduced changes that occur in the capacitance–voltage (C–V) response of an organic metal–insulator–semiconductor (MIS) capacitor based on the organic semiconductor poly(3-hexylthiophene), P3HT. During the forward voltage sweep, the device is driven into deep depletion but stabilizes at a voltage-independent minimum capacitance, C_min, whose value depends on photon energy, light intensity and voltage ramp rate. On reversing the voltage sweep, strong hysteresis is observed owing to a positive shift in the flatband voltage, V_FB, of the device. A theoretical quasi-static model is developed in which it is assumed that electrons photogenerated in the semiconductor depletion region escape geminate recombination following the Onsager model. These electrons then drift to the P3HT/insulator interface where they become deeply trapped thus effecting a positive shift in V_FB. By choosing appropriate values for the only disposable parameter in the model, an excellent fit is obtained to the experimental C_min, from which we extract values for the zero-field quantum yield of photoelectrons in P3HT that are of similar magnitude, 10^?5 to 10^?3, to those previously deduced for π-conjugated polymers from photoconduction measurements. From the observed hysteresis we deduce that the interfacial electron trap density probably exceeds 10¹⁶ m^?2. Evidence is presented suggesting that the ratio of free to trapped electrons at the interface depends on the insulator used for fabricating the device.     

提高超小型铝电解电容器生产一次合格率

恰当选择原材料、确保铆接工序质量、重视工作电解液的配比、严控各工序成品率是提高超小型铝电解电容器投入产出一次合格率的关键。以１０Ｖ－４７μＦ（４ｍｍ×７ｍｍ）产品为例，投入产出一次合格率达９４％以上。     

球形触点阵列与四边扁平封装的比较

球形触点阵列（ＢＧＡ）封装技术作为一种新的封装技术越来越受到人们的重视。从安装率和成本、表面安装印制板设计以及焊点可靠性三个方面对球形触点阵列与四边扁平封装（ＱＦＰ）进行了比较。分析认为，ＢＧＡ和ＱＦＰ各有其优势和劣势，各有其应用重点。     

广州市东濠涌流域低影响开发措施雨洪控制效应评估

随着我国城市化进程的快速推进和海绵城市理念的不断加深,低影响开发(LID)措施日益受到各地重视。为评估LID措施的雨洪控制效果,构建基于SWMM的东濠涌流域城市雨洪模型,分析选取适合该研究区域的LID措施,分别采用重现期为0.5、1、2、5、10年的设计降雨对LID措施的雨洪控制效应进行分析。研究结果表明:LID措施能够较为有效地减小流域洪峰流量、径流量及推迟峰值时间,对初期雨水径流污染负荷也具有较好的削减作用,且径流量和污染物削减率均随着重现期增大而减小。     

水驱油藏产油量递减率影响因素的分解方法——以锦州9-3油田和渤海油田的应用为例

从递减率定义出发,建立了水驱油藏产油量递减率与综合含水率、采油速度、含水上升率、产液量变化率4个影响因素之间的变化关系式,提出一种产油量递减率影响因素分解方法。通过该方法可以量化每个影响因素对产油量递减率的贡献大小,明确产油量递减率的主要影响因素,为油田下步调整挖潜、减缓递减的措施提供依据。应用表明,该方法能够满足油田实际产液量变化要求,且具有简单、方便、可操作性强的特点,易于矿场的推广应用。     

降低焦炭塔操作压力对焦化过程的影响

考察了降低焦炭塔操作压力对延迟焦化过程的影响。中试结果表明：在炉出口温度、注汽量、循环比等操作条件基本一致的情况下,当焦炭塔的操作压力由0.195MPa降低到0.115MPa时,气体和焦炭的产率降低,液体产品收率提高且表现在焦化蜡油收率的提高上,二者分别提高了2.03百分点和4.64百分点;随着操作压力的降低,焦化汽油和焦化柴油的性质基本一致,但焦化蜡油性质变差,主要表现在密度、残炭、沥青质、氮含量及金属等均有所升高,95%馏出温度提高14℃;石油焦的挥发分呈降低趋势。