基于二次反锐化掩模的多特征侧扫 声纳成像海底底质分类

提出了一种二次反锐化掩模算子(QUM),用于从图像中提取等比重的边缘和细节信息.把图像的平均边缘细节量(QUM )、平均纹理能量(TEM )和标准差(σ)相结合,构成本文的三维特征矢量(QUM ,TEM ,σ),用于对侧扫声纳海底图像进行底质分类.利用该特征矢量(QUM ,TEM ,σ)对泥、沙、石三种类型海底的150幅侧扫声纳图像进行分类实验,获得了最高96.7%、最低90.7%的识别率,而利用常用的灰阶共生矩阵方法的分类识别率为87.3%,表明本文方法能较好地用于海底底质分类.     

高成品率砷化镓DPDT单片射频开关

采用砷化镓 76mm 0 .7μm离子注入 MESFET工艺技术研制出手机用砷化镓 DPDT单片射频开关(以下简称单片开关 )。该单片开关面积 1 3 1 0 μm× 1 2 5 0 μm,总栅宽 3 6mm,工作频率 DC～ 2 GHz,1 GHz下插入损耗 IL小于 0 .5 2 d B,隔离度 ISO大于 1 7d B,驻波 VSWR≤ 1 .3 ,2 GHz下 IL小于 0 .7d B,ISO大于 1 1 d B,驻波≤ 1 .3 ,反向三阶交调 PTOI优于 64 d Bm,1 W射频信号下的栅漏电小于 2 0 μA。连续五批共 60片的统计结果表明 ,该单片开关圆片上芯片的直流成品率最低 84 % ,最高 96% ;微波参数成品率在 75 %～ 86%之间 ,代表着国内 Ga As单片电路成品率的最高水平     

现代电子工业Cpk评价中的特殊问题

现代电子工业生产具有许多新的特点，如果不针对具体情况，均采用传统工业生产中广泛使用的常规方法计算其工序能力指数，评价生产工艺水平，将可能导致错误的结论。总结了电子工业生产中工艺参数的典型特点，并讨论了工序能力指数的正确计算方法。     

An Integrated CAD Methodology for Yield Enhancement of VLSI CMOS Circuits Including Statistical Device Variations

In this paper a novel CAD methodology for yield enhancement of VLSI CMOS circuits including random device variations is presented. The methodology is based on a preliminary characterization of the technological process by means of specific test chips for accurate mismatch modeling. To this purpose, a very accurate position-dependent parameter mismatch model has been formulated and extracted. Finally a CAD tool implementing this model has been developed. The tool is fully integrated in an environment of existing commercial tools and it has been experimented in the STMicroelectronics Flash Memory CAD Group.As an example of application, a bandgap reference circuit has been considered and the results obtained from simulations have been compared with experimental data. Furthermore, the methodology has been applied to the read path of a complex Flash Memory produced by STMicroelectronics, consisting of about 16,000 MOSFETs. Measurements of electrical performances have confirmed the validity of the methodology, and the accuracy of both the mismatch model and the simulation flow.     

多变量工序能力指数系统模型

工序能力最终决定微电子工艺的质量水平。工序能力指数确定能够有效地确保微电子工艺水平。随着微电子工艺水平的快速发展,工艺趋于复杂化,工艺水平评价需要关注一个以上的特征参数。因此,传统的单变量工序能力指数不能有效综合的分析工序的水平。本论文提出了一个多变量工序能力指数模型系统。这个模型系统包括针对数据满足多变量正态分布的域多变量工序能力指数;针对数据不满足多变量正态分布的因子多变量工序能力指数;以及成品率多变量工序能力指数。最后通过实例分析算验证这些多变量工序能力指数是有效和实用的。     

Ultrathin Highly Luminescent Two‐Monolayer Colloidal CdSe Nanoplatelets

Surface effects in atomically flat colloidal CdSe nanoplatelets (NLPs) are significantly and increasingly important with their thickness being reduced to subnanometer level, generating strong surface related deep trap photoluminescence emission alongside the bandedge emission. Herein, colloidal synthesis of highly luminescent two‐monolayer (2ML) CdSe NPLs and a systematic investigation of carrier dynamics in these NPLs exhibiting broad photoluminescence emission covering the visible region with quantum yields reaching 90% in solution and 85% in a polymer matrix is shown. The astonishingly efficient Stokes‐shifted broadband photoluminescence (PL) emission with a lifetime of ≈100 ns and the extremely short PL lifetime of around 0.16 ns at the bandedge signify the participation of radiative midgap surface centers in the recombination process associated with the underpassivated Se sites. Also, a proof‐of‐concept hybrid LED employing 2ML CdSe NPLs is developed as color converters, which exhibits luminous efficacy reaching 300 lm W_opt^?1. The intrinsic absorption of the 2ML CdSe NPLs (≈2.15 × 10⁶ cm^?1) reported in this study is significantly larger than that of CdSe quantum dots (≈2.8 × 10⁵ cm^?1) at their first exciton signifying the presence of giant oscillator strength and hence making them favorable candidates for next‐generation light‐emitting and light‐harvesting applications.     

Simulation Techniques for the Manufacturing Test of MCMs

Simulation techniques used in the Manufacturing Test SIMulator(MTSIM) are described. MTSIM is a Concurrent Engineering tool used tosimulate the manufacturing test andrepair aspects of boards and MCMs from design concept through manufacturing release. MTSIM helps designers select assemblyprocess, specify Design For Test (DFT) features, select board testcoverage, specify ASIC defect level goals, establish productfeasibility, and predict manufacturing quality and cost goals. A newyield model for boards and MCMs which accounts for theclustering of solder defects is introduced and used topredict the yield at each test step. In addition, MTSIMestimates the average number of defects per board detected at eachtest step, and estimates costs incurred in test execution, faultisolation and repair. MTSIM models were validated withhigh performance assemblies at Hewlett-Packard (HP).     

超深亚微米可制造标准单元库设计

当集成电路的特征尺寸下降到100nm以下,可制造性设计就变得尤为重要。本文提出了一种65nm可制造性标准单元库的设计方法。通过精简基本单元的数量,降低光学矫正的时间和空间复杂度;利用DFM设计规则和光学模拟仿真对每个单元的版图进行优化以提高整个单元库的可制造性。应用该方法实现的标准单元库在时序,功耗,面积方面与传统标准单元库相比具有很好的性能,并且通过Foundry的TD部门65nm工艺线的可制造性测试,有利于65nm工艺生产良率的提升。     

Energy yield prediction errors and uncertainties of different photovoltaic models

Mathematical, empirical, and electrical models have long been implemented and used to predict the energy yield of many photovoltaic (PV) technologies. The purpose of this paper is to compare the annual DC energy yield prediction errors of four models namely the single‐point efficiency, single‐point efficiency with temperature correction, the Photovoltaic for Utility‐Scale Applications (PVUSA), and the one‐diode model, against outdoor measurements for different grid‐connected PV systems in Cyprus over a 4‐year evaluation period. The different models showed a wide variation of prediction errors, demonstrating a strong dependence between model performance and the different technologies. In particular, it was clearly shown that the application of temperature loss correction based on the manufacturer's temperature coefficients of power at maximum power point assisted in improving the energy yield prediction significantly especially for the crystalline silicon (c‐Si) technologies. In most cases, the best agreement between the modeled results and outdoor‐measured annual DC energy yield for mono‐crystalline silicon (mono‐c‐Si) and multi‐crystalline silicon (multi‐c‐Si) technologies was obtained using the one‐diode model. The energy yield for the thin‐film technologies was more accurately predicted using the PVUSA model with the exception of the copper‐indium‐gallium‐diselenide (CIGS) technology, which was best predicted using the single‐point efficiency with temperature correction and one‐diode models, thus demonstrating similar physical properties to c‐Si technologies. The paper further quantifies the combined uncertainties associated with the predicted energy yield as a function of the input parameters for the single‐point efficiency, single‐point efficiency with temperature correction, and the PVUSA models. Copyright © 2011 John Wiley & Sons, Ltd.     

基于人工神经网络的高分五号高光谱影像悬浮泥沙浓度反演方法

悬浮泥沙浓度是水体监测中极为重要的指标.本论文基于神经网络具有弥补传统经验算法固有误差的潜力,设计并开发了基于人工神经网络的神经网络校正器来对经验反演结果进行二次校正.为了防止在小数据集的情况下出现过拟合问题,采用了特殊设计的正则化项.基于高分五号高光谱遥感数据以及在长江口和沿海水域同时收集的悬浮泥沙浓度实地测量结果,...