机器人离散滑模变结构—PI控制器

本文采用离散滑模变结构控制方法，针对机器人提出了一种滑模变结构——ＰＩ控制方案，给出了该控制方案滑模存在条件及控制器设计方案。该控制器将离散滑模变结构控制和ＰＩ控制两者的优点有机地结合起来，理论分析和仿真结果表明该控制器能使机器人在各种复杂非线性动力学情况下具有良好的性能指标。这种控制器输出切换小，可以投入应用。     

Superplastic behaviour of Ti-48at.%Al two-phase titanium aluminide compacts made from mechanically alloyed powder

An HIP compact of MA-processed powder having a nominal composition of Ti-48at.% Al was produced. The compact consisted of a large amount of TiAl(λ) and a small amount of Ti₃Al (₂), in a completely ultra-fine equiaxed grain structure. This two-phase compact showed typical superplastic deformation behaviour. A maximum elongation of 550% was obtained. A strain exponent, n = 2, and grain size exponent, p = 2, were determined from the results of a strain-rate-change test and a creep test at constant initial stress using samples having various grain sizes, respectively. The activation energy for creep, Q_c at constant stress was calculated to be 350 kJ/mole. It is concluded that the superplastic deformation mechanism of the material under study is grain boundary sliding controlled by lattice diffusion in the TiAl phase.     

OFDM技术及其应用

首先对OFDM的发展以及应用做了简要的介绍,然后讨论了当前OFDM研究过程中的两个关键技术问题,最后展望了OFDM的未来发展。     

n-Al2O3/Ni复合镀层的组织与滑动磨损性能研究

用电刷镀技术制得了镍基n-Al2O3复合镀层，并对镀层的滑动磨损性能进行了试验研究。纳米复合镀层的表面形貌比较细腻，镀层中纳米粒子分布均匀，与基质金属结合紧密。镀层显微硬度达到HV700，比快速镍镀层提高约40％。滑动磨损试验结果表明，随着纳米粒子含量的增大，镀层的耐磨性提高，摩擦系数也呈增大趋势；但当镀层中n-Al2O3粒子的超过2.56%(质量分数）时，镀层的耐磨性显著下降。纳米复合镀层的磨损机制以疲劳磨损为主，而快速镍底层以粘着磨损为主。     

Experience with Applying Formal Methods to Protocol Specification and System Architecture

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intel's processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.     

用C++ Builder实现数字图像的平滑处理

介绍了图像增强技术中，空间域处理方法中的邻域平均法的原理、算法，及该原理在windows平台上以C＋＋ Builder为开发工具的具体程序实现。     

Influence of load and speed on wear characteristics of grey cast iron in dry sliding — selection for minimum wear

The wear of grey cast iron in dry sliding conditions has been studied with the aims of (1) finding the influence of working conditions on the wear rate, and (2) determining the region of speed and load where low wear is accomplished. Grey cast iron with flake and nodular graphite was submitted to investigation using a pin-on-disc machine. The results indicate that the flake graphite cast iron is more suitable for applications at speeds greater than 4 m s⁻¹ and lower loads, while nodular cast iron has greater wear resistance at lower speeds in the range of loads investigated - from 50 N cm⁻² to 200 N cm⁻²     

攀钢“501”滑动水口液压驱动系统的研制

介绍了为攀钢“５０１”滑动水口研制的专用液压驱动系统，对该系统的工作原理，性能特点，主要元件（设备）的选择原则等作了较为详细的说明介绍。     

EDA介质快慢横波时差和振幅-方位曲线的实验分析

在含垂直定向裂隙的各向异性（EDA）介质中，地震快、慢横波传播的时差及振幅随裂隙（缝）方位变化曲线能反映裂缝的密度、走向和介质的性质，这对多波地震资料的处理、解释有着重要意义。但受观测条件限制以及噪声的影响，在横波分裂记录上，同相轴往往会出现扭曲、倾斜和不规则抖动等现象，给快、慢横波时差的求取和振幅-方位曲线的绘制带来误差。设计了EDA介质物理模型，并利用岩石超声波测量系统获得了快、慢横波记录；分析记录可知，在相同传播方向的分裂横波具有走时和传播速度不随裂缝方位变化的恒定性特征；以此为基础，提出了利用平均法和瞬时振幅法来计算快、慢横波的走时时差和绘制振幅-方位曲线，以提高精度。利用物理模型实验得到的2个正交横波（S1波与S2波）的快、慢横波记录，分别用平均法和瞬时振幅法计算了快、慢横波走时的平均值、时差和均方差，并绘制了相应的振幅一方位曲线。结果表明，采用上述2种方法，消除了同相轴扭曲、倾斜和不规则抖动等对计算结果的影响，时差的计算是可靠的，振幅一方位曲线的绘制是合理的。     

Reducing Average and Peak Test Power Through Scan Chain Modification

Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result in frequent transitions in the scan chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the scan chain can help reduce transitions while loading the test vector needed. The transitions embedded in both test stimuli and the responses are handled through scan chain modifications consisting of logic gate insertion between scan cells as well as inversion of capture paths. No performance degradation ensues as these modifications have no impact on functional execution. To reduce average and peak power, we herein propose computationally efficient schemes that identify the location and the type of logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.