A BIST-DFT technique for DC test of analog modules

Among test techniques for analog circuits, DC test is one of the simplest method for BIST application since easy to integrate test pattern generator and response analyzer are conceivable. Precisely, this paper presents such an investigation for a CMOS operational amplifier that is latter extended to active analog filters. Since the computation of fault coverage is still a controversy question for analog cells, we develop first an evaluation technique for optimizing the tolerance band of the measurements to test. Then, using some DFT solutions we derive single DC pattern and discuss the minimal number of points to test for the detection of defects. A response analyzer is integrated with a Built-in Voltage Sensor (BIVS) and provides directly a logic pass/fail test result. Finally, the extra circuitry introduced by this BIST technique for analog modules does not exceed 5% of the total silicon area of the circuit under test and detects most of the faults.     

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

On the Realization of Current－Mode Continuous－Time Operational Transconductance Capacitance Filter

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乙醇柴油混合燃料的应用研究

介绍了乙醇与柴油在助溶剂的作用下形成稳定期较长的混合燃料-E10和E15,它们的理化性质与普通柴油接近。在不对柴油机作改动设计的情况下,进行实车运行试验,柴油机动力性能下降幅度不大,燃料消耗增加不多,同时排烟有明显改善,说明乙醇燃料具有良好的应用前景。     

一种基于时空编码的物理层安全算法

针对多天线窃听系统的物理层安全问题,提出一种基于时空编码的预编码算法。首先,合法接收者发送训练序列用于发送者估计主信道状态信息,而窃听信道的状态信息合法用户均未知;其次,发送者利用均匀信道分解的方法提取主信道状态信息的特征参数,生成发射端预编码矩阵和合法接收端均衡矩阵,收发联合加密处理提高物理层安全;最后,利用 Monte Carlo方法进行仿真实验,数值分析表明,该算法在窃听者天线数目增多时能够实现非负的保密容量,即使窃听信道质量较好时,窃听者的接收性能仍维持在很差的水平,误码率高达0.5。     

1.9～5.7 GHz宽带低噪声BiCMOS LC VCO

设计了一种宽带、低相位噪声差分LC压控振荡器(VCO)。所设计的电路采用开关电容阵列和开关电感,实现了多波段振荡输出。对负阻环节跨导进行了优化设计,将热噪声控制在最小范围内,同时采用高品质因数片上螺旋电感,以减小电路的噪声干扰。采用台积电(TSMC)0.35μmSiGe BiCMOS工艺制作了流片,并进行了仿真和硬件电路实验。实测结果表明,当调谐电压为0～3.3 V时,可设定VCO工作在6个波段(1.9～2.1 GHz,2.1～2.4 GHz,2.4～3.0 GHz,3.0～3.4 GHz,3.4～4.2 GHz,4.2～5.7 GHz),此6波段连续可调,构成了1.9～5.7 GHz宽带VCO;VCO的中心频率为2.4 GHz、偏离中心频率为1 MHz时实测相位噪声为-111.64 dBc/Hz;在3.3 V电源电压下实测核静态电流约为1.8 mA,从而验证了宽带、低噪声BiCMOS LC VCO设计方案之正确性。     

音频功率放大器的CMOS电路设计

完成了一种桥式连接音频功率放大器的仿真和设计。该音频功率放大器的主体为桥式连接的两个运算放大器,使用尽可能小的外部组件提供高质量的输出功率,不需要输出耦合电容、 自举电容和缓冲网络。应用Cadence的Spectre模拟仿真工具进行电路仿真,得到其电路指标如频响特性、电源电压抑制比、总谐波失真等均达到要求。该音频功率放大器具有良好的市场应用前景。     

基于Matlab的模拟滤波器设计与仿真

巴特沃思、切比雪夫模拟低通滤波器通常是设计模拟高通、带通和带阻滤波器的原型,先按给定频率响应巴特沃思、切比雪夫低通Ha（s）逼近,然后由选定Ha（s）实现二端口网络的电路结构和参数值。在此对达林顿T型和П型电路结构的滤波器元件参数进行了编程计算,并对其系统函数的幅频特性进行仿真。仿真结果符合设计要求,该方法便捷,程序具有可扩展性。     

一个1.2伏CMOS0.13微米工艺19.2毫瓦10位30兆采样率流水线模数转换器

A 10-bit 30-MS/s pipelined analog-to-digital converter (ADC) is presented. For the sake of lower power and area, the pipelined stages are scaled in current and area, and op amps are shared between the successive stages. The ADC is realized in the 0.13-μ m 1-poly 8-copper mixed signal CMOS process operating at 1.2-V supply voltage. Design approaches are discussed to overcome the challenges associated with this choice of process and supply voltage, such as limited dynamic range, poor analog characteristic devices, the limited linearity of analog switches and the embedded sub-1-V bandgap voltage reference. Measured results show that the ADC achieves 55.1-dB signal-to-noise and distortion ratio, 67.5-dB spurious free dynamic range and 19.2-mW power under conditions of 30 MSPS and 10.7-MHz input signal. The FoM is 0.33 pJ/step. The peak integral and differential nonlinearities are 1.13 LSB and 0.77 LSB, respectively. The ADC core area is 0.94 mm².     

Thermal stability of Hfl'aON films prepared by physical vapor deposition

We investigate the thermal stability of HfTaON films prepared by physical vapor deposition using high resolution transmission electronic microscope (HRTEM) and X-ray photoelectron spectroscopy (XPS). The results indicate that the magnetron-sputtered HtTaON films on Si substrate are not stable during the post-deposition an-healing (PDA). HfTaON will react with Si and form the interfacial layer at the interface between HfTaON and Si substrate. Hf-N bonds are not stale at high temperature and easily replaced by oxygen, resulting in significant loss of nitrogen from the bulk film. SiO2 buffer layer introduction at the interface of HfTaON and Si substrate may effec-tively suppress their reaction and control the formation of thicker interfacial layer. But SiO2 is a low k gate dielectric and too thicker SiO2 buffer layer will increase the gate dielectric's equivalent oxide thickness. SiON prepared by oxidation of N-implanted Si substrate has thinner physical thickness than SiO2 and is helpful to reduce the gate dielectric's equivalent oxide thickness.