集成电路芯片级的热分析方法

文章在研究分析了集成电路中功耗的主要来源以及温度对集成电路性能的影响后，详细总结了近年来集成电路芯片级的几种热分析方法。并从实际应用角度对这几种方法进行了分析和比较，讨论了各个方法的优点及其适用范围。     

UAV-assisted multi-hop D2D relaying for communication in large disaster area

An unmanned aerial vehicle (UAV)-assisted communication is a promising technique for enabling ground users in a non-functional area (NFA) or disaster area to communicate. All the base stations in the disaster area may be partially or fully damaged due to the natural calamity. Device-to-device (D2D) communication can be a viable solution for immediate connection between users in an NFA. We propose a UAV-assisted multi-hop D2D communication following a hybrid power-time switching (PTS) in this paper. Moreover, a D2D user of a cluster can communicate with another D2D user in a different cluster through UAVs. However, D2D users can harvest energy from their respective ad hoc energy stations and forward the information to the nearby D2D user following a hybrid PTS-based strategy. We propose a time frame for the same and show a node-based energy harvesting strategy. The expressions of outage probability, throughput, end-to-end energy consumption, and energy efficiency are developed for the Rician and Nakagami-m faded channel. The impact of several network parameters such as energy harvesting factor, energy harvesting efficiency, and fading parameter on the network performance is also indicated.     

低功耗自动灌溉控制器设计

自动灌溉控制技术是农业物联网发展的方向之一,为了快速、准确感知土壤湿度实现节约型灌溉,在此设计了一种由德州仪器公司提供的低功耗单片机Launchpad为核心的自动灌溉控制器。该控制器利用Arduino土壤湿度传感器模块对土壤湿度值进行监测,能够及时显示湿度数据信息,并对灌溉设备水泵进行有效的开关控制,从而达到节水的目的。经过多次实验,测试采样数据准确,控制效果好,有比较大的推广价值。     

Interfacial reaction between 42Sn-58Bi solder and electroless Ni-P/immersion Au under bump metallurgy during aging

The interfacial reaction between 42Sn-58Bi solder (in wt.% unless specified otherwise) and electroless Ni-P/immersion Au was investigated before and after thermal aging, with a focus on the formation and growth of an intermetallic compound layer, consumption of under bump metallurgy (UBM), and bump shear strength. The immersion Au layer with thicknesses of 0 μm (bare Ni), 0.1 μm, and 1 μm was plated on a 5-μm-thick layer of electroless Ni-P (with 14–15 at.% P). The 42Sn-58Bi solder balls were then fabricated on three different UBM structures by using screen printing and pre-reflow. A Ni₃Sn₄ layer formed at the joint interface after the pre-reflow for all three UBM structures. On aging at 125°C, a quaternary phase, identified as Sn₇₇Ni₁₅Bi₆Au₂, was observed above the Ni₃Sn₄ layer in the UBM structures that contain Au. The thick Sn₇₇Ni₁₅Bi₆Au₂ layer degraded the integrity of the solder joint, and the shear strength of the solder bump was about 40% less than the nonaged joints.     

Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box

Cryptographic substitution boxes (S-boxes) are an integral part of modern block ciphers like the Advanced Encryption Standard (AES). There exists a rich literature devoted to the efficient implementation of cryptographic S-boxes, wherein hardware designs for FPGAs and standard cells received particular attention. In this paper we present a comprehensive study of different standard-cell implementations of the AES S-box with respect to timing (i.e. critical path), silicon area, power consumption, and combinations of these cost metrics. We examine implementations which exploit the mathematical properties of the AES S-box, constructions based on hardware look-up tables, and dedicated low-power solutions. Our results show that the timing, area, and power properties of the different S-box realizations can vary by up to almost an order of magnitude. In terms of area and area-delay product, the best choice are implementations which calculate the S-box output. On the other hand, the hardware look-up solutions are characterized by the shortest critical path. The dedicated low-power implementations do not only reduce power consumption by a large degree, but they also show good timing properties and offer the best power-delay and power-area product, respectively.     

Negative capacitance independent multi-gate FinFETs and their optimisations

In order to reduce the operating voltage of FinFET and increase the flexibility of integrated circuit design, we have proposed a Negative Capacitance Independent Multi-Gate FinFET (NC-IMG-FinFET) with Ferroelectric-Metal-Insulator-Semiconductor-Insulator (FMISI) structure. Both the device and circuit analysis model of NC-IMG-FinFET are addressed, which are used to analyse the performance parameters of the device (the surface potential, internal gate voltage amplification, Sub-threshold Swing (SS), on-current and leakage) and the performance of a circuit (delay, power consumption, power delay product (PDP)). The simulation model of the NC-IMG-FinFET has been constructed by combining BSIM-IMG model with ferroelectric Landau-Khalatnikov model. The optimisations for ferroelectric film thickness of the NC-IMG-FinFETs are carried out in terms of device characteristics and circuit performances. The simulation results are consistent with the analysis results, indicating that the NC-IMG-FinFET has superior performance compared with the baseline device, in terms of smaller leakage, larger on/off current ratio and smaller SS (38.3 mV/dec at room temperature). Compared with the baseline IMG-FinFET circuits, there is large performance improvement for the NC-IMG-FinFET circuits, in terms of the power consumption and PDP.     

Analysis of Power Consumption on Laser Solder Joints of Electric Connector

Laser soldering process was introduced in Universal serial bus （USB） 2.0 electric connector to improve the mechanical and electrical bonding reliabil- ity. While, the effects of laser soldering technology on electric connector solder joints need to be estimated com- pletely, especially on power consumption. The combined method based on numerical simulation and the Accelerated temperature experiment （ATE） was developed to analyze the power consumption of USB 2.0 electric connector in this paper. The ATE contains thermal cycle and thermal shock tests, and the four-electrode method is used to ob- tain the conductivity of solder joints. Numerical modeling and analysis was used to quantify the power consumption and optimize the geometry of solder joints, because the electric experimental measurements of power consumption during ATE are time-costing and often intractable. Accurate knowledge of the power consumption is a prerequisite for the reliability of the electric connector.     

通过改进TFT-LCD生产工艺提高光透过率降低生产成本和能耗

很多人都把注意力集中在TFT液晶显示器的面板技术上,例如LED背光源、120/240Hz帧频、宽视角以及其它一些能提高显示性能的技术。在这个背景下,通过不断改进TFT液晶显示器的制造工艺,提高了生产效率,降低了成本,同时亦提高了能源利用率。最新的技术进展涉及滤光片、液晶配向、TFT设计等方面。     

Ultra-low power m-sequence code generator for body sensor node applications

In this paper, a design of low power m-sequence code generator is proposed. The efficiency of producing the code sequence within the region of sub-threshold voltage is investigated using 90 nm technology and verified using the auto-correlation and eye diagram characterizations. A further method of power saving in addition to voltage reduction is carried out by scaling the technology node from 90 to 65 nm. A comparison of power consumption and maximum attainable frequency between both technologies is performed. The ratio of power saving while using 65 nm technology is ranging from 45% to 55% for the three different code lengths investigated.     

加权选举的无线传感器网络协议

为了提高无线传感器网络的稳定期,提出了一种高效节能的加权选举协议。该协议使用集群策略结合链状路由算法,在异构的无线传感器网络环境下改善节能并且延长稳定期。仿真结果表明该协议在网络寿命和稳定期方面的性能都优于LEACH,SEP和HEARP。另外,实验表明在异构环境下稳定期依赖于节点的额外能量。