不同注F剂量与CMOS运放电路辐照损伤的相关性

在不同注F剂量条件下,对P沟和N沟两种不同差分对输入CMOS运放电路的电离辐照响应进行了研究.分析比较了注F和未注F运放电路电离辐照响应之间的差异.结果表明,在栅场介质注入适量的F,可有效抑制辐照感生的氧化物电荷尤其是界面态的增长,从而提高CMOS运放电路的抗辐照特性.     

Grouped Approach for the Design of H.264/AVC Motion Estimation Architectures

This letter presents a novel approach for organizing computational resources into groups within H.264/AVC motion estimation architectures, leading to reductions of up to 75% in the equivalent gate count with respect to state‐of‐the‐art designs.     

STI process steps for sub-quarter micron CMOS

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μ CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.     

Effective lightning protection schemes for distribution line

The causes of lightning outage are subdivided into direct lightning strokes and induced lightning strokes, which are identified by the characteristics of the lightning overvoltage. In the past, lightning protection devices were directed mainly toward the latter, and attention has been focused on the installation of lightning protection devices, ground wires, and reinforcement of insulators. However, lightning outages continue to occur. Thus it is extremely important to clarify the fault characteristics of lightning surges and to study the effectiveness of various lightning protection devices by considering both direct lightning stroke and induced lightning stroke in order to prevent lightning outage in the future. In this research, the electromagnetic transients program (EMTP) has been applied to the direct lightning stroke, and the induced lightning outage analysis program for multiple conductor systems has been applied to the induced lightning stroke to study the effectiveness of lightning protection devices provided by combination of various lightning protection devices. The most effective lightning protection schemes are analyzed and evaluated based on verification tests on the full scale models as well as economic considerations.     

一种3V CMOS音乐集成电路的设计原理

介绍了一种数字式全定制音乐集成电路设计原理。对伪音阶发生器、节拍发生器等子电路作了较详细的叙述。采用这种原理可设计出单芯片驱动压电陶瓷和发光二极管的音乐集成电路，该电路无须外接电阻、电容，可存储数首歌曲；另外，还可设计出一种数字音频程控频率合成器，时钟为ｆ０时，可控频率范围为ｆ０２～ｆ０２Ｎ。     

差分式连续时间电流型CMOS跨导—电容低通滤波器

应用信号流图法对电流系统传递函数直接模拟，提出了一种新颖的差分式连续时间电流模式ＣＭＯＳ跨导－电容低通滤波器的实现方案。由于采用了差分式结构和电流负反馈，整个电路方案具有差分式结构和电流型电路的优点；并且仅使用最少数量的ＯＴＡ和电容，与数字ＣＭＯＳ工艺兼容，适于全集成。面向实际电路完成了ＭＯＳ管级的计算机仿真，结果表明，所提出的电路方案正确有效     

CMOS电路中抗Latch-up的保护环结构研究

闩锁是CMOS集成电路中的一种寄生效应,这种PNPN结构一旦被触发,从电源到地会产生大电流,导致整个芯片的失效。针对芯片在实际测试中发现的闩锁问题,介绍了闩锁的测试方法,并且利用软件Tsuprem4和Medici模拟整个失效过程,在对2类保护环(多子环/少子环)作用的分析,以及各种保护结构的模拟基础之上,通过对比触发电压和电流,得到一种最优的抗Latch up版图设计方法,通过进一步的流片、测试,解决了芯片中的闩锁失效问题,验证了这种结构的有效性。     

混合集成型光学拾音器的设计与制作

通过混合集成型结构光学拾音器的光学设计和芯片设计，制作了包含微光学棱镜，光电探测器和信号放大电路的混合集成型光学拾音器。经过测试，发现有较好的信号输出特性，表明混合集成型光学拾音器已基本研制成功。     

Formation of low-resistivity poly-Si and SiNx films by Cat-CVD for ULSI application

In this paper, bulk-Si metal–oxide–semiconductor field effect transistors (MOSFETs) are fabricated using the catalytic chemical vapor deposition (Cat-CVD) method as an alternative technology to the conventional high-temperature thermal chemical vapor deposition. Particularly, formation of low-resistivity phosphorus (P)-doped poly-Si films is attempted by using Cat-CVD-deposited amorphous silicon (a-Si) films and successive rapid thermal annealing (RTA) of them. Even after RTA processes, neither peeling nor bubbling are observed, since hydrogen contents in Cat-CVD a-Si films can be as low as 1.1%. Both the crystallization and low resistivity of 0.004 Ω·cm are realized by RTA at 1000 °C for only 5 s. It is also revealed that Cat-CVD SiN_x films prepared at 250 °C show excellent oxidation resistance, when the thickness of films is larger than approximately 10 nm for wet O₂ oxidation at 1100 °C. It is found that the thickness required to stop oxygen penetration is equivalent to that for thermal CVD SiN_x prepared at 750 °C. Finally, complementary MOSFETs (CMOSs) of single-crystalline Si were fabricated by using Cat-CVD poly-Si for gate electrodes and SiN_x films for masks of local oxidation of silicon (LOCOS). At 3.3 V operation, less than 1.0 pA μm⁻¹ of OFF leakage current and ON/OFF ratio of 10⁷–10⁸ are realized, i.e. the devices can operate similarly to conventional thermal CVD process.     

Modular implementation of efficient self-checking checkers for the Berger code

A technique for designing efficient checkers for conventional Berger code is proposed in this paper. The check bits are derived by partitioning the information bits into two blocks, and then using an addition array to sum the number of 1's in each block. The check bit generator circuit uses a specially designed 4-input 1's counter. Two other types of 1's counters having 2 and 3 inputs are also used to realize checkers for variable length information bits. Several variations of 2-bit adder circuits are used to add the number of 1's. The check bit generator circuit uses gates with fan-in of less than or equal to 4 to simplify implementation in CMOS. The technique achieves significant improvement in gate count as well as speed over existing approaches.