FPGA配置芯片测试方法的研究与实现

集成电路规模越来越大,测试难度也越来越高,边界扫描方法的提出降低了测试的复杂度,适合进行大规模集成电路的测试。介绍了边界扫描的概念和特点,研究了FPGA配置芯片测试方法,并在V93000测试系统上实现了配置芯片EPC2的边界扫描测试,给出了具体测试过程,符合IEEE1149.1边界扫描规范,为具有JTAG接口的元器件测试提供了依据。     

基于JTAG的DSP处理器嵌入式调试接口设计

介绍了基于IEEE1149．1 JTAG协议的DSP处理器嵌入式调试接口的设计。从该接口的整体结构框图到详细设计，进行了详细的阐述。该接口成功地应用于32bits DSP处理器MD32中，通过了FPGA验证和仿真验证，证明了其设计的正确性，具有很好的参考价值。     

边界扫描测试技术及其应用

边界扫描技术是一种完整的、标准化的可测性设计方法，它提供了对电路板上元件的功能、互连等进行测试的一种统一方案，极大地提高了系统测试的效率。本文详细介绍了边界扫描测试的原理、结构，讨论了边界扫描测试技术的应用。     

从边界扫描技术协议讨论其发展与应用

边界扫描测试技术作为当前电子测试技术的热点,其应用与发展是令人瞩目的。本文通过对边界扫描技术一系列协议的简单介绍和剖析,讨论了边界扫描技术各个阶段的应用与发展情况,并对边界扫描技术未来的发展给出了一些预测。     

基于JTAG的矢量生成型边界扫描架构设计与实现

在结合IEEE1149.1标准的基础上,利用半跳变(Half Transition,HT)模型的基本思想,提出新的HTF模型新的矢量施加方式,在此基础上构建了实现基于JTAG的矢量生成型边界扫描架构.该架构的设计思路为:在兼容1149.1的基础上,通过自定义SI测试指令,实现JTAG对信号完整性测试的支持,拓展了边界扫描的应用范围.     

基于JTAG的线路板测试性设计研究

本文讨论了边界扫描测试性设计原理和方法.研究了线路板互连故障模型.并对故障模型进行了一些简化测试的等效处理.建立了边界扫描测试数学模型。基于这些模型,原理和方法.提出了两种优化的边界扫描互连测试算法。然后用边界扫描测性设计方法进行线路板的测试性设计.两种优化算法的正确性和有效性得到了验证。     

Interconnect Delay Fault Test on Boards and SoCs with Multiple Clock Domains

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system‐on‐chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.     

Multi-TAP Controller Architecture for Digital System Chips

This paper describes an architecture for controlling multiple IEEE 1149.1 compliant TAP controllers on a single digital system chip. The key feature of this architecture is the compatibility with the IEEE 1149.1 standard, and existing debugger software. Results are presented, obtained from an experiment, in which the proposed architecture is mapped on an FPGA to control multiple existing designs with TAP controllers.     

ATPG and diagnostics for boards implementing boundary scan

The emergence of the IEEE 1149.1 boundary scan standard facilitates structured approaches for board partitioning, allowing test generation and execution on localized logic clusters. This article discusses a study conducted on 1149.1 board designs to examine issues associated with board-level Automatic Test-Pattern Generation (ATPG) and diagnostics.