一种遵循IEEE 1149.1标准的可测试性设计结构

IEEE ll49．1(也称JTAG)是支持芯片边界扫描的国际标准，提供了统一的测试访问端口。如今，它已成为芯片必不可少的一种“开销”。本文通过定制JTAG逻辑，以求用最少的开销，最简单灵活的方式来管理各种DFT逻辑。     

Efficient board interconnect testing using the split boundary scan register

This article presents a new approach to testing board interconnects, on a board containing chips equipped with the Boundary Scan Architecture. The proposed technique reduces the test time, test vector size, and requires an order independent test set at the expense of minimal hardware overhead to the ANSI/IEEE Std. 1149.1-1990 standard. Although most of the algorithms developed so far can be used to test boards under this scheme, we have concentrated on the Walking 1's and 0's for the purpose of presenting this technique. This test can be applied with a reduced time complexity for test generation and application. Furthermore, with local response compaction this scheme can easily be used for BIST implementation, resulting in the application of Walking 1/0 in linear time. All of the above results assume boards that contain 3-state nets, which is an improvement over previously reported results.     

An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1

ANSI/IEEE Std 1149.1 defines a standard implementation of boundary scan that, it is hoped, will be built into many catalog and application-specific integrated circuits. The standard was developed as a solution to two continuing trends that are having a significant, adverse, impact on the task of testing loaded printed wiring boards: increasing chip complexity and greater miniaturization. The former increases the difficulty of test generation, while the latter impedes access for the bed-of-nails and hand-held probes on which many established test techniques depend.This tutorial provides a guide to the principal features defined by the standard and to their operation. It is intended as a prelude to the standard itself, not as a substitute for it. In particular, it is recommended that readers who intend to implement integrated circuits, design tools, or test systems that support the standard read the standard document before doing so.     

基于IEEE 1149.1标准的可重定向片上调试方法

介绍了一种基于IEEE1149．1标准的可重定向的调试方法，详细地分析了一种嵌入式调试模块的内部结构、工作原理、实现过程以及它给处理器核带来的代价，该模块在RTL级只需较少的修改即可集成在多种微处理器核上．完成片上调试的功能。     

基于MTM总线的边界扫描控制器设计与实现

超大规模集成电路和组装工艺快速发展,电路板结构和功能日趋复杂,将边界扫描技术应用于系统级测试,对提高系统的可靠性和可维护性具有重要的实用意义;在深入研究IEEE1149.5和IEEE1149.1标准的基础上,对基于MTM总线的边界扫描控制器结构进行了研究,解决了IEEE1149.5与IEEE1149.1协议转换中的关键技术,设计实现了内嵌边界扫描功能的MTM总线从模块,使用SpartanⅡ器件实现了基于MTM总线的边界扫描控制器;仿真和实验结果表明,IEEE1149.5总线接口、IEEE1149.1端口和TAP控制器功能正确,符合系统层次化测试的实际要求。     

基于SOPC的边界扫描测试控制器IP核设计

在研究边界扫描数字电路测试技术标准IEEE1149.1的基础上,采用SOPC设计技术,用FPGA设计实现了一款基于Avalon总线的边界扫描测试总线控制IP核,与其它复用IP核可形成以NIOS Ⅱ处理器为核心的通用数字电路边界扫描测试控制器,该控制器产生符合IEEE1149.1标准的测试信号控制被测边界扫描系统,进行各种边界扫描测试;该IP核的成功设计,为基于边界扫描的电子系统机内自测试系统的实现,奠定了坚实的应用基础。     

嵌入式处理器在片调试功能的设计与实现

以龙芯1号处理器为研究对象,探讨了嵌入式处理器中在片调试功能的设计实现方法.通过扩充IEEEP1149.1协议的JTAG测试访问端口（TAP）,并在处理器内部增加控制模块,实现了软件调试断点、调试中断、硬件断点以及单步执行等多种在片调试功能.调试主机只需要通过一根JTAG调试电缆就可以访问目标处理器内部寄存器等各种资源,并控制目标处理器的运行过程,实现了处理器的在片调试功能,大大地方便了软件开发与系统调试.     

基于JTAG控制器Net-1149.1的测试系统模型

讨论了建立基于JTAG控制器Net-1149．1的测试系统模型的基本方法和系统结构。介绍了测试环境软硬件平台的建立及在测试主机上的软件编程及调试工作。     

IEEE1149.1产生新标准

研制边界扫描原先是为了检验IC引线与PCB连接轨迹，现在它已被用于支持芯片调试、设备流程，混合信号测试和现场服务。     

基于IEEE1149.7的新一代测试接口实现与应用

随着芯片集成度的不断增加和对低功耗设计的重视,原初开发的JTAG（IEEE STD1149.1）面对新的挑战,不能满足当今设计的需要。CJTAG基于IEEE STD1149.7标准和传统的JTAG的边界扫描原理来提供一个更加强大的测试和调试的标准,来达到现在系统的要求。CJTAG用更少的管脚来提供更多的功能,而同时保证了对IEEE1149.1的软件和硬件的兼容性。