基于边界扫描技术的集成电路测试系统设计与实现

介绍了边界扫描的技术原理,及其在集成电路测试中的具体应用,并给出了一种基于边界扫描技术的板级集成电路测试系统的方案及实现。     

边界扫描技术在高速列车信号控制电路板测试与诊断中的应用

中国最近几年对高速铁路的投入和重视程度举世瞩目.列车作为高速铁路的运输载体,其质量尤为重要,控制系统中的信号控制板作为高速列车的“大脑”,其可靠性直接决定了整车的安全性.由于大量采用BGA、QFP封装的FPGA、DSP芯片导致测试途径有限、测试覆盖率较低等缺点,提出了将边界扫描技术与PXI总线标准仪器相结合的方法,对信号控制板进行有效的测试,可显著提高测试覆盖率并实现元器件级的故障诊断,同时减少测试时间.     

基于JTAG标准的边界扫描在通用CPU中的设计

剖析了JTAG标准的精髓，分析了其组成，功能与时序控制等关键技术，结合一款通用CPU的具体要求，给出了一种实现JTAG结构的具体方法，并介绍了其功能测试的方法。     

An Implementation Approach of the IEEE 1149.1 for the Routing Test of a VLSI Massively Parallel Architecture

This paper presents an implementation approach for the test of routers in a fine grain massively parallel architecture. First, an ad hoc test technique which diffuses test messages router by router is analyzed. Even though the technique does not add hardware, it is shown inefficient and not applicable due to practical constraints such as the limited number of pins of the chip implementing the machine. Based on a hierarchical implementation of the IEEE 1149.1 standard, two approaches are proposed and compared in terms of the area overhead, the overall test time and the flexibility in applying tests and diagnosing the routers inside the machine. The basic idea for both approaches is to construct groups of basic cells which are driven by the same test block and compare their test results after the same test vectors are applied at each cell input. The two approaches differ in the granularity of a basic cell. The choice of an implementation approach is not trivial. It is shown that each approach presents better performance than the other, that is, the approach which allows better fault coverage and less test time requires more silicon and less diagnostic possibilities compared to the second approach.     

边界扫描测试的软件实现

随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。该文在分析IEEE JTAG标准和并口标准的基础上，设计开发了边界扫描测试软件。引入Access为后台数据库，实现了多种芯片的故障检测功能；介绍了边界扫描测试的基本原理和结构；讲述了BST软件设计中精确时钟控制、管脚查找、显示管脚波形等设计方法。以Altera的ep1c6q240器件为例，介绍了整个边界扫描测试过程。     

基于边界扫描技术的SOC数字电路可测性设计

随着SOC系统的快速发展,如何对其进行有效的测试与诊断是当前研究的热点问题。从SOC数字电路可测试性设计的角度出发,基于边界扫描技术,设计了具有边界扫描结构的IP核,并对相应的测试方法进行了研究。通过仿真及时序分析,验证了该设计方法的可行性,为SOC系统的测试提供了新的思路。